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You can use the Compiler to process any design in an open project. With the Compiler, you can perform the following types of compilation on a design:
With the Analyze Current File command (Processing menu), you can check the current design file for syntax errors using the Database Builder module of the Compiler.
With the Start > Start Analysis & Elaboration command (Processing menu), you can check all the design files in a design for syntax and semantic errors, and perform a netlist extraction. This command uses the Database Builder module of the Compiler.
With the Start > Start Analysis & Synthesis command (Processing menu), you can check all the design files in a design for syntax and semantic errors, perform netlist extraction, and synthesize and perform technology mapping on the logic of the design. This command uses the Database Builder and Logic Synthesizer modules of the Compiler.
With the Start Compilation command (Processing menu), you can perform a full compilation of a design. With this command, you can also perform a smart compilation, which can help future recompilations run faster, or a fast fit compilation, which increases compilation speed for a design by up to 50%.
With the Start > Start SignalProbe™ command (Processing menu), you route signals in a compiled design to user-specified signals of a design. With this command, you can debug specific signals without having to perform a full compilation.
To stop an analysis, analysis and elaboration, analysis and synthesis, or compilation, use the Stop Processing command (Processing menu).
In the Compiler, you compile a design by compiling a design entity using its associated group of Compiler settings. Therefore, to specify a design to compile, you specify a design entity and a group of Compiler settings.
You specify the design entity you want to compile by setting that entity as the compilation focus. When you compile the design, you compile the compilation focus and all the design entities below that focus. The compilation focus can be any top-level or lower-level design entity in a project; however, when you set a lower-level design entity as the compilation focus, and do not set the lower-level design entity as a new top-level design entity, the lower-level design entity inherits parameter and assignment settings from the higher-level entities in its hierarchy.
You specify the Compiler settings to use for the compilation by specifying a group of settings as the current Compiler settings. You can use the Compiler Settings wizard or the pages under the Compiler Settings page in the Settings dialog box (Assignments menu) to edit any group of Compiler settings, or you can use the default Compiler settings that are generated automatically each time you create a new project. You can also create a new group of Compiler settings for a project; when you create new Compiler settings, the settings automatically become the current Compiler settings.
Prior to compiling a design, you can specify any of the following settings that apply to the design:
Related Timing Analyzer settings. Go to Overview: Using the Timing Analyzer for more information on the Timing Analyzer.
User libraries for the design.
Options for compiling Verilog Design Files (.v). Go to Overview: Using the Quartus® II Software with Other EDA Tools for information on specifying options for Verilog Design Files that are optimized and synthesized by an EDA tool. Use the Verilog HDL Input page of the Settings dialog box (Assignments menu) to specify options for compiling Verilog Design Files directly with the Compiler.
Options for compiling VHDL Design Files (.vhd). Go to "Overview: Using the Quartus II Software with other EDA Tools" for information on specifying options for VHDL Design Files that are optimized and synthesized by an EDA tool. Use the VHDL Input page of the Settings dialog box to specify options for compiling VHDL Design Files directly with the Compiler.
Options for compiling EDIF Input Files (.edf), Verilog Quartus® Mapping Files (.vqm), and Text Design Files (.tdf) created by EDA tools. Go to "Overview: Using the Quartus II Software with Other EDA Tools" for more information on specifying these options.
Options for creating Verilog Output Files (.vo) and VHDL Output Files (.vho). Go to "Overview: Using the Quartus II Software with Other EDA Tools" for more information on specifying Verilog HDL and VHDL output settings.
Related SignalProbe compilation settings. Go to SignalProbe Feature Introduction for more information on the SignalProbe feature.
Related Design Assistant settings. Go to Overview: Using the Design Assistant for more information on the Design Assistant.
If you want to recompile a design without using any compilation information (for example, database files) that may exist in the database from a previous compilation of the design, you can specify the design's Compiler settings as the current Compiler settings and choose Purge Compiler Results from Database (Processing menu). You can also use this command to delete compilation results you no longer need. When you purge compilation results from the database, you lose all results of the design's compilation, including the Compilation Report for the design and any information saved during a "smart compilation."
You can save synthesis results for an entity to a VQM File by setting the compilation focus to that entity, turning on Incremental Synthesis, and then compiling.
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