An ASCII text file (with the extension .vhd or .vhdl) created with the Quartus^® II Text Editor or another standard text editor. A VHDL Design File contains design logic that is defined with VHDL.

A VHDL Design File can contain any combination of the VHDL 1987 or 1993 constructs supported by the Quartus II software. For more information, see "Quartus II VHDL Support."

You can easily incorporate primitives, Altera-provided and user-defined megafunctions, and user-defined macrofunctions into a VHDL Design File. You can use a logic function by creating a component in the file or in a referenced package and using a Component Instantiation Statement to insert an instance of the logic function. You can also use this method to incorporate VHDL logic into another VHDL Design File. Some Altera-provided primitives can also be expressed as logical operators in Boolean expressions.

A single VHDL Design File can be used to define all logic in a project, or can be incorporated at any hierarchy level in a hierarchical project. In the Text Editor, you can create a Block Symbol File (.bsf) or an AHDL Include File (.inc) that represents a VHDL Design File with the Create/Update > Create Symbol Files for Current File and Create/Update > Create AHDL Include Files for Current File commands (File menu), respectively. You can incorporate a BSF into a Block Design File (.bdf), and an AHDL Include File into a AHDL Text Design File (.tdf) or Verilog Design File (.v).

The Quartus II Compiler can also create VHDL Output Files (.vho) for use with other EDA tools.

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