Compiler

Synthesis Page (Settings Dialog Box)
NOTE You can open this page from the Settings dialog box (Assignments menu).

Allows you to specify options for logic synthesis.

Pointer Click any item in this picture for information on that item:


Files & Directories page HDL Input Settings EDA Tool Settings Default Logic Option Settings Default Parameter Settings Timing Settings General Page Device Page Mode page Fitting page STII Logic Analyzer page Design Assistant Netlist Optimizations Simulator Settings page Software Build Settings page Stratix GX Registration page HardCopy Settings page OK Cancel Save node-level netlist Compiler SEttings


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