Compiler

Mode Page (Compiler Settings) (Settings Dialog Box)
NOTE You can open this page from the Settings dialog box (Assignments menu).

Allows you to specify options that control the level of compilation, the compilation speed, and the amount of disk space used for compilation. This page also allows you to automatically route SignalProbe signals during compilation, modify the latest fitting results during a SignalProbe compilation, and use back-annotated routing constraints during compilation.

Pointer Click any item in this picture for information on that item:


Compiler Settings Files & Directories page HDL Input Settings EDA Tool Settings Default Logic Option Settings Default Parameter Settings Timing Settings General Page Device Page Synthesis page Fitting page STII Logic Analyzer page Design Assistant Netlist Optimizations Simulator Settings page Software Build Settings page Stratix GX Registration page HardCopy Settings page OK Cancel Compilation speed/disk usage tradeoff Preserve fewer node names Automatically route SP during compilation Modify latest fitting results during SP Read routing constraints Mode Page


Back to Top

- PLDWorld -

 
Created by chm2web html help conversion utility.