Procedures

Commands

See Also

Incremental synthesis allows you to save synthesis results for individual entities in the project hierarchy and reuse those results in other projects. Incremental synthesis reduces compilation times and enhances support for system-on-a-programmable-chip (SOPC) design flows.

When you compile with Incremental synthesis in the Synthesis page in the Settings dialog box (Assignments menu) turned on, the Quartus^® II software saves an ATOM-based netlist for the current compilation focus to a Verilog Quartus^® Mapping File (.vqm).

You can use the VQM File as the entity's source file when you instantiate the entity in a new project. When you compile an entity from a VQM File or other ATOM-based netlist, you ensure that node names within the entity remain the same, regardless of other entities in the design. For this reason, Altera^® recommends that you use incremental synthesis when you export LogicLock^™ region assignments from one project and import them into another project. By using incremental synthesis to generate a VQM File for an entity when you export its assignments, and by instantiating the entity from the VQM File in the project where you import the assignments, you ensure that the node names synthesized in the new project correspond to the node names in the imported assignments.

Incremental synthesis provides a framework for modular, team-oriented design. Using incremental synthesis, you can design a block of custom logic or instantiate a block of pre-verified intellectual property (IP), make assignments to that block, verify functionality and performance, and "lock" the block to maintain this placement and performance. In this way, blocks can be designed, tested and optimized individually and maintain their performance when integrated into a larger design.

If you are already compiling from EDIF Input Files (.edf) or VQM Files, which are ATOM-based netlists, you do not need to perform incremental synthesis with the Quartus II software.

Back to Top