In this lecture => modeling combinational logic for synthesis
logical
and arithmetical operations-assignments
logical
structure control for synthesis process
synthetisable
models of multiplexers
synthetisable
models of encoders and priority encoders
synthetisable
models of decoders and address decoders
generic
models of decoders and comparators
an
arithmetical and logic unit with a multiplexer
as well as
tri-state buffers
generated from one and several
processes
in
the next lecture (7), we will study the synthesisable models of synchronous
logic such as latches, flip-flops, registers and counters
