Modeling tri-state buffers from several processes using if statement
library IEEE;
use IEEE.std_logic_1164.all; entity tri_state_1 is port (a,b,c,d: in std_logic; ea,eb,ec,ed: in std_logic; x: in std_logic); end tri_state_1; |
architecture
several_processes of
tri_state_1 is
begin A: process (a,ea) begin if (ea='1') then x <= a; else x <= 'Z'; end if; end process A; -- process B -- process C D: process (d,ed) begin if (ed='1') then x <= d; else x <= 'Z'; end if; end process D; end several_processes; |