TRI-STATE BUFFERS - one process

 

signals with multiple sources connected to one destination point may be implemented using tri-state buffers

tri-state buffers are modeled using conditional assignments or multi-way branch statements like case or if .. then ..else ..

the tri-state buffer is inferred by assigning a high impedance state (Z) to a signal which is not selected by a particular condition

multiple buffers connected to the same destination point must be modeled in separate concurrent statements

Modeling tri-state buffers with conditional signal assignments

 
library IEEE; 

use IEEE.std_logic_1164.all;

entity tri_state_1 is

    port (a,b,c,d: in std_logic; ea,eb,ec,ed: in std_logic; x: in std_logic);
end tri_state_1; 
 
architecture simple of tri_state_1 is 

begin

x <= a when (ea='1') else 'Z';
x <= b when (eb='1') else 'Z';
x <= c when (ec='1') else 'Z';
x <= d when (ed='1') else 'Z';

end simple;