ALUs

arithmetic-logic units consist of purely combinational logic circuits and perform a set of arithmetic and logic operation on two input busses

the operation to be performed is encoded on n selection lines to indicate up to 2n different micro-operations

(see numeric_std package)

Operation table of an ALU

function block s4 s3 s2 s1 s0 cin operation
transfer a

increment a

addition

add with acrry

a plus 1's comp. of b

subtraction

decrement a

transfer a

and

or

xor

comp. a

transfer a

shift left a

shift right a

transfer 0

 AU

AU

AU

AU

AU

AU

AU

AU

LU

LU

LU

LU

SHU

SHU

SHU

SHU

 0..0..0..0..0..0..

0..0..0..0..0..1..

0..0..0..0..1..0..

0..0..0..0..1..1..

0..0..0..1..0..0..

0..0..0..1..0..1..

0..0..0..1..1..0..

0..0..0..1..1..1..

0..0..1..0..0..0..

0..0..1..0..1..0..

0..0..1..1..0..0..

0..0..1..1..1..0..

0..0..0..0..0..0..

0..1..0..0..0..0..

1..0..0..0..0..0..

1..1..0..0..0..0..

 x <= a

x <= a +1

x <= a + b

x <= a + b + 1

x <= a + b'bar

x <= a + b'bar +1

x <= a - 1

x <= a

x <= a and b

x <= a or b

x <= a xor b

x <= a'bar

x <= a

x <= shl a

x <= shr a

x <= 0

ALU entity

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

entity alu is

    port (s: in unsigned(4 downto 0); a,b: in unsigned (15 downto 0); x: out unsigned (15 downto 0);cin: in std_logic);

end alu;

architecture data_flow of alu is

begin

process(s,a,b,cin)

    variable s0_1_cin: unsigned(2 downto 0);

    variable lu,au,alu_nsh: unsigned(7 downto 0);

begin

-- AU

    s0_1cin := s(1 downto 0) & cin;

    a_unit:case s0_1_cin is

      when "000" => au := a;

      when "001" => au := a + 1;

      when "010" => au := a + b;

      when "011" => au := a + b + 1;

      when "100" => au := a + not b;

      when "101" => au := a - b;

      when "110" => au := a - 1;

      when "111" => au := a;

      when others => au := (others=>'X');

    end case a_unit;

-- LU

    l_unit:case s(1 downto 0) is

      when "00" => lu := a and b;

      when "01" => lu := a or b;

      when "10" => lu := a xor b;

      when "11" => lu := not a;

      when others => lu := (others =>'X');

    end case l_unit;

-- MUX: multiplexing au and lu outputs

    la_mux: if (s(2)='1') then

        alu_nsh := lu;

      else

        alu_nsh := au;

      end if la_mux;

-- shifter

    sh_unit: case s(4 downto 3) is

      when "00" => x <= alu_nsh;

      when "01" => x <= sll(alu_nsh,1);

      when "10" => x <= srl(alu_nsh,1);

    -- these functions are defined in numeric_std package

      when "11" => x <= (others=>'X');

    end case sh_unit;

end process;

end data_flow;

Exercise:

Draw the corresponding schematics with 4 blocks : AU, LU, MUX, SHU