use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

entity data_flow is

port(a1: in unsigned(7 downto 0);

-- unsigned is defined in IEEE.numeric_std

a2,b2,c2,d2: in unsigned(3 downto 0);

y1: out std_logic;

y2: out unsigned(8 downto 0));

end data_flow;

signal s1,s2: std_logic;

begin

P1: process(a1(3 downto 0)) -- full sensitivity list

variable tmp: unsigned(1 downto 0);

begin

tmp := ((a1(0) and a1(1)) , (a1(2) and a1(3)));

-- tmp := sequential assignment inferring connection

s1 <= tmp(0) or tmp(1);

end process P1;

P2: process(a1(7 downto 4))

variable tmp: unsigned(1 downto 0);

begin

tmp := (a1(4) and a1(5)) & (a1(6) and a1(7));

-- tmp := sequential assignment inferring connection

s2 <= tmp(0) or tmp(1);

end process P2;

y1 <= s1 xor s2; -- concurrent signal

P3: process(a2,b2,c2,d2)

begin

y2 <= a2*(b2+c2) - d2;

-- adders and multiplier circuit are inferred;

-- not an efficient solution

end process P3;

end simple;