parantheses
and optimization
Parantheses may be used to control (impose) the structure of adder (long versus short delay)
| library IEEE;
use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity comb_logic is port(a,b,c,d: in unsigned(16 downto 0); y: out unsigned(18 downto 0)); end comb_logic; |
The following model infers three adders and a sequence of three addition steps:
| architecture
simple_1 of comb_logic
is
begin process(a,b,c,d) -- full sensitivity list begin y <= a + b + c + d; end process; end simple_1; -- three addition steps |
The following model infers three adders and a sequence of two addition steps:
| architecture
simple_2 of comb_logic
is
begin process(a,b,c,d) -- full sensitivity list begin y <= (a + b) + (c + d); end process; end simple_2; -- two addition steps |
