Generic binary decoders

 

the use of VHDL generic and component instantiation -> generic decoders with n-bit input and m-bit output defined at instantiation phase (structural model)

the use of generic functions and data flow architecture -> generic decoders with n-bit input and m-bit output defined with the generic function call (data_flow model)

Structural model
 
library IEEE; 

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity dec_gen is

    generic (size_in, size_out: integer);
    port (e: in std_logic; a: in unsigned (size_in-1 downto 0); 
      x: out unsigned(size_out-1 downto 0));
end dec_gen; 
 
architecture process_dec_gen of dec_gen is 
begin
process(a)
begin
    if (e='0') then x <= (others=>'0');
    else
      for i in 0 to size_out-1 loop
        if (to_integer(a)=i) then
        x(i) <='1';
        else
        x(i) <='0';
        end if;
      end loop;
    end if;
end process;

end process_dec_gen;

and its instantiations in a structural architecture of a higher level entity:
 
library IEEE; 

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity str_dec_gen is

    port (e_a, e_b: in std_logic; 
      in_a: in unsigned (4 downto 0); 
      in_b: in unsigned (7 downto 0); 
      out_a: out unsigned(31 downto 0);
      out_b: out unsigned(255 downto 0));
end str_dec_gen; 
 
architecture structural of str_dec_gen is 

component dec_gen is

    generic (size_in, size_out: integer);
    port (e: in std_logic; a: in unsigned (size_in-1 downto 0); 
      x: out unsigned(size_out-1 downto 0));
end component; 

begin

decoder_5to32:dec_gen -- decoder_5to32 instantiation

      generic map(5, 32)
      port map(e_a, in_a, out_a);
decoder_8to256:dec_gen -- decoder_8to256 instantiation
      generic map(8, 256)
      port map(e_b, in_b, out_b);
end structural;

Functional model

a package with a decoder function:
 
library IEEE; 

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

package dec_gen_pack is
function gen_dec(e:std_logic; a:unsigned; size_in,size_out-1:integer) return unsigned;
end dec_gen_pack;

package body dec_gen_pack is

function gen_dec(e:std_logic; a:unsigned; size_in,size_out:integer) return unsigned is
variable: tmp: unsigned(size_out-1 downto 0);

begin

    if (e='0' or to_integer(a) > sizeout-1) then tmp <= (others=>'0');
    else
      for i in 0 to size_out-1 loop
        if (to_integer(a)=i) then
        tmp(i) :='1';
        else
        tmp(i) :='0';
        end if;
      end loop;
    end if;
    return tmp;
end gen_dec;

end dec_gen_pack;

and an entity with data_flow architecture and function calls
 
library IEEE; 

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use work.dec_gen_pack.all;

entity fun_dec_gen is

    port (e_a, e_b: in std_logic; 
      in_a: in unsigned (4 downto 0); 
      in_b: in unsigned (7 downto 0); 
      out_a: out unsigned(31 downto 0);
      out_b: out unsigned(255 downto 0));
end fun_dec_gen; 
 
architecture data_flow_dec of fun_dec_gen is 

begin

process(e_a,in_a,e_b,in_b)

    begin

    -- two function calls (instead of two instantiations)

      out_a <= gen_dec(e_a,in_a,5,32);

      out_b <= gen_dec(e_b,in_b,8,256);

    end process;
end data_flow_dec;