Chapter 1 Designing Microprocessors
1.1 Overview of a Microprocessor 3 1.2 Design Abstraction Levels 6 1.3 Examples of a 2-to-1 Multiplexer 6 1.3.1 Behavioral Level 7 1.3.2 Gate Level 8 1.3.3 Transistor Level 9 1.4 Introduction to VHDL 9 1.5 Synthesis 12 1.6 Going Forward 12 1.7 Summary Checklist 13 1.8 Problems 13
Chapter 2 Digital Circuits
2.1 Binary Numbers 3 2.2 Binary Switch 5 2.3 Basic Logic Operators and Logic Expressions 6 2.4 Truth Tables 7 2.5 Boolean Algebra and Boolean Function 8 2.5.1 Boolean Algebra 8 2.5.2 * Duality Principle 10 2.5.3 Boolean Functions and their Inverses 10 2.6 Minterms and Maxterms 13 2.6.1 Minterms 14 2.6.2 * Maxterms 15 2.7 Canonical, Standard, and non-Standard Forms 17 2.8 Logic Gates and Circuit Diagrams 17 2.9 Designing a Car Security System 20 2.10 VHDL for Digital Circuits 22 2.10.1 VHDL code for a 2-input NAND gate 22 2.10.2 VHDL code for a 3-input NOR gate 23 2.10.3 VHDL code for a function 24 2.11 Summary Checklist 25 2.12 Problems 26
Chapter 3 Combinational Circuits
3.1 Analysis of Combinational Circuits 3 3.1.1 Using a Truth Table 3 3.1.2 Using a Boolean Function 6 3.2 Synthesis of Combinational Circuits 7 3.3 * Technology Mapping 9 3.4 Minimization of Combinational Circuits 12 3.4.1 Karnaugh Maps 12 3.4.2 Don’t-cares 17 3.4.3 * Tabulation Method 18 3.5 * Timing Hazards and Glitches 19 3.5.1 Using Glitches 21 3.6 BCD to 7-Segment Decoder 21 3.7 VHDL for Combinational Circuits 23 3.7.1 Structural BCD to 7-Segment Decoder 24 3.7.2 Dataflow BCD to 7-Segment Decoder 28 3.7.3 Behavioral BCD to 7-Segment Decoder 28 3.8 Summary Checklist 30 3.9 Problems 31
Chapter 4 Standard Combinational Components
4.1 Signal Naming Conventions 3 4.2 Adder 3 4.2.1 Full Adder 3 4.2.2 Ripple-carry Adder 5 4.2.3 * Carry-lookahead Adder 6 4.3 Two’s Complement Binary Numbers 7 4.4 Subtractor 9 4.5 Adder-Subtractor Combination 11 4.6 Arithmetic Logic Unit 13 4.7 Decoder 18 4.8 Encoder 20 4.8.1 * Priority Encoder 21 4.9 Multiplexer 21 4.9.1 * Using Multiplexers to Implement a Function 24 4.10 Tri-state Buffer 24 4.11 Comparator 26 4.12 Shifter 29 4.12.1 * Barrel Shifter 31 4.13 * Multiplier 31 4.14 Summary Checklist 33 4.15 Problems 34
Chapter 5 Implementation Technologies
5.1 Physical Abstraction 3 5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) 4 5.3 CMOS Logic 5 5.4 CMOS Circuits 6 5.4.1 CMOS Inverter 6 5.4.2 CMOS NAND Gate 7 5.4.3 CMOS AND Gate 8 5.4.4 CMOS NOR and OR Gates 10 5.4.5 Transmission Gate 10 5.4.6 2-input Multiplexer CMOS Circuit 10 5.4.7 CMOS XOR and XNOR Gates 12 5.5 Analysis of CMOS Circuits 13 5.6 * Using ROMs to Implement a Function 14 5.7 * Using PLAs to Implement a Function 16 5.8 * Using PALs to Implement a Function 20 5.9 * Complex Programmable Logic Device (CPLD) 22 5.10 * Field Programmable Gate Array (FPGA) 24 5.11 Summary Checklist 25 5.12 Problems 25
Chapter 6 Latches and Flip-Flops
6.1 Bistable Element 3 6.2 SR Latch 4 6.3 SR Latch with Enable 6 6.4 D Latch 7 6.5 D Latch with Enable 8 6.6 Clock 9 6.7 D Flip-Flop 10 6.7.1 * Alternative Smaller Circuit 11 6.8 D Flip-Flop with Enable 12 6.9 Asynchronous Inputs 13 6.10 Description of a Flip-Flop 14 6.10.1 Characteristic Table 14 6.10.2 Characteristic Equation 14 6.10.3 State Diagram 15 6.10.4 Excitation Table 15 6.11 * Timing Issues 15 6.12 Car Security System—Version 2 16 6.13 VHDL for Latches and Flip-Flops 17 6.13.1 Implied Memory Element 17 6.13.2 VHDL Code for a D Latch with Enable 18 6.13.3 VHDL Code for a D Flip-Flop 18 6.13.4 VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear 21 6.14 * Other Flip-Flop Types 22 6.14.1 SR Flip-Flop 22 6.14.2 JK Flip-Flop 23 6.14.3 T Flip-Flop 24 6.15 Summary Checklist 25 6.16 Problems 25
Chapter 7 Sequential Circuits
7.1 Finite State Machine (FSM) Models 3 7.2 State Diagrams 5 7.3 Analysis of Sequential Circuits 8 7.3.1 Excitation Equation 9 7.3.2 Next-state Equation 9 7.3.3 Next-state Table 9 7.3.4 Output Equation 10 7.3.5 Output Table 10 7.3.6 State Diagram 11 7.3.7 Analysis of a Moore FSM 11 7.3.8 Analysis of a Mealy FSM 13 7.4 Synthesis of Sequential Circuits 15 7.4.1 State Diagram 15 7.4.2 Next-state Table 16 7.4.3 Implementation Table 18 7.4.4 Excitation Equation and Next-state Circuit 19 7.4.5 Output Table and Equation 19 7.4.6 FSM Circuit 19 7.4.7 Synthesis of Moore FSMs 19 7.4.8 Synthesis of a Mealy FSM 25 7.5 Unused State Encodings and the Encoding of States 27 7.6 Designing a Car Security System—Version 3 30 7.7 VHDL for Sequential Circuits 31 7.8 * Optimization for Sequential Circuits 37 7.8.1 State Reduction 37 7.8.2 State Encoding 38 7.8.3 Choice of Flip-Flops 39 7.9 Summary Checklist 42 7.10 Problems 42
Chapter 8 Standard Sequential Components
8.1 Registers 3 8.2 Shift Registers 5 8.2.1 Serial-to-Parallel Shift Register 5 8.2.2 Serial-to-Parallel and Parallel-to-Serial Shift Register 7 8.3 Counters 9 8.3.1 Binary Up Counter 10 8.3.2 Binary Up-down Counter 12 8.3.3 Binary Up-down Counter with Parallel Load 14 8.3.4 BCD Up Counter 15 8.3.5 BCD Up-down Counter 16 8.4 Register Files 18 8.5 Static Random Access Memory 22 8.6 * Larger Memories 26 8.6.1 More Memory Locations 26 8.6.2 Wider Bit Width 26 8.7 Summary Checklist 29 8.8 Problems 29
Chapter 9 Datapaths
9.1 Designing Dedicated Datapaths 4 9.1.1 Selecting Registers 7 9.1.2 Selecting Functional Units 8 9.1.3 Data Transfer Methods 9 9.1.4 Generating Status Signals 10 9.2 Using Dedicated Datapaths 11 9.3 Examples of Dedicated Datapaths 11 9.3.1 Simple IF-THEN-ELSE 12 9.3.2 Counting 1 to 10 13 9.3.3 Summation of n Down to 1 15 9.3.4 Factorial of n 16 9.3.5 Count 0’s and 1’s 18 9.4 General Datapaths 20 9.5 Using General Datapaths 21 9.6 A More Complex General Datapath 23 9.7 Timing Issues 27 9.8 VHDL for Datapaths 29 9.8.1 Dedicated Datapath 29 9.8.2 General Datapath 30 9.9 Summary Checklist 35 9.10 Problems 35
Chapter 10 Control Units
10.1 Constructing the Control Unit 4 10.1.1 Counting 1 to 10 4 10.1.2 Simple IF-THEN-ELSE 8 10.2 Generating Status Signals 14 10.3 Stand-Alone Controllers 22 10.3.1 Rotating Lights 22 10.3.2 PS/2 Keyboard Controller 26 10.3.3 VGA Monitor Controller 30 10.4 * ASM Charts and State Action Tables 41 10.4.1 ASM Charts 41 10.4.2 State Action Tables 44 10.5 VHDL for Control Units 45 10.6 Summary Checklist 46 10.7 Problems 48
Chapter 11 Dedicated Microprocessors
11.1 Manual Construction of a Dedicated Microprocessor 4 11.2 Examples of Manual Designs for Dedicated Microprocessors 8 11.2.1 Greatest Common Divisor 8 11.2.2 Summing Input Numbers 15 11.2.3 High-Low Guessing Game 20 11.2.4 Finding the Largest Number 26 11.3 VHDL for Dedicated Microprocessors 32 11.3.1 FSM + D Model 32 11.3.2 FSMD Model 37 11.3.3 Behavioral Model 39 11.4 Summary Checklist 40 11.5 Problems 40
Chapter 12 General-Purpose Microprocessors
12.1 Overview of the CPU Design 3 12.2 The EC-1 General-Purpose Microprocessor 4 12.2.1 Instruction Set 4 12.2.2 Datapath 5 12.2.3 Control Unit 6 12.2.4 Complete Circuit 10 12.2.5 Sample Program 11 12.2.6 Simulation 13 12.2.7 Hardware Implementation 13 12.3 The EC-2 General-Purpose Microprocessor 14 12.3.1 Instruction Set 14 12.3.2 Datapath 15 12.3.3 Control Unit 16 12.3.4 Complete Circuit 19 12.3.5 Sample Program 20 12.3.6 Hardware Implementation 22 12.4 VHDL for General-Purpose Microprocessors 23 12.4.1 Structural FSM+D 23 12.4.2 Behavioral FSMD 30 12.5 Summary Checklist 33 12.6 Problems 33
Appendix A Schematic Entry Tutorial 1
A.1 Getting Started 2 A.1.1 Preparing a Folder for the Project 2 A.1.2 Starting MAX+plus II 2 A.1.3 Starting the Graphic Editor 3 A.2 Using the Graphic Editor 4 A.2.1 Drawing Tools 4 A.2.2 Inserting Logic Symbols 4 A.2.3 Selecting, Moving, Copying, and Deleting Logic Symbols 5 A.2.4 Making and Naming Connections 6 A.2.5 Selecting, Moving and Deleting Connection Lines 8 A.3 Specifying the Top-Level File and Project 8 A.3.1 Saving the Schematic Drawing 8 A.3.2 Specifying the Project 8 A.4 Synthesis for Functional Simulation 8 A.5 Circuit Simulation 9 A.5.1 Selecting Input Test Signals 9 A.5.2 Customizing the Waveform Editor 10 A.5.3 Assigning Values to the Input Signals 11 A.5.4 Saving the Waveform File 11 A.5.5 Starting the Simulator 12 A.6 Creating and Using the Logic Symbol 13
Appendix B VHDL Entry Tutorial 2
B.1 Getting Started 2 B.1.1 Preparing a Folder for the Project 2 B.1.2 Starting MAX+plus II 2 B.1.3 Creating a Project 3 B.1.4 Editing the VHDL Source Code 4 B.2 Synthesis for Functional Simulation 4 B.3 Circuit Simulation 5 B.3.1 Selecting Input Test Signals 5 B.3.2 Customizing the Waveform Editor 7 B.3.3 Assigning Values to the Input Signals 8 B.3.4 Saving the Waveform File 8 B.3.5 Starting the Simulator 8
Appendix C UP2 Programming Tutorial 3
C.1 Getting Started 2 C.1.1 Preparing a Folder for the Project 2 C.1.2 Creating a Project 3 C.1.3 Viewing the Source File 3 C.2 Synthesis for Programming the PLD 4 C.2.1 Selecting the Target Device 4 C.2.2 Synthesis 4 C.3 Circuit Simulation 5 C.4 Maping the I/O Pins with the Floorplan Editor 7 C.5 Fitting the Netlist and Pins to the PLD 9 C.6 Hardware Setup 10 C.6.1 Installing the ByteBlaster Driver 10 C.6.2 Jumper Settings 10 C.6.3 Hardware Connections 10 C.7 Programming the PLD 11 C.8 Testing the Hardware 13 C.9 MAX7000S EPM7128SLC84-7 Summary 13 C.9.1 JTAG Jumper Settings 14 C.9.2 Prototyping Resources for Use 14 C.9.3 General Pin Assignments 15 C.9.4 Two Push-Button Switches 15 C.9.5 16 DIP Switches 15 C.9.6 16 LEDs 16 C.9.7 7-Segment LEDs 16 C.9.8 Clock 16 C.10 FLEX10K EPF10K70RC240-4 Summary 17 C.10.1 JTAG Jumper Settings 17 C.10.2 Prototyping Resources for Use 17 C.10.3 Two Push-Button Switches 17 C.10.4 8 DIP Switches 17 C.10.5 7-Segment LEDs 18 C.10.6 Clock 18 C.10.7 PS/2 Port 18 C.10.8 VGA Port 18
Appendix D VHDL Summary
D.1 Basic Language Elements 2 D.1.1 Comments 2 D.1.2 Identifiers 2 D.1.3 Data Objects 2 D.1.4 Data Types 2 D.1.5 Data Operators 5 D.1.6 ENTITY 6 D.1.7 ARCHITECTURE 6 D.1.8 GENERIC 7 D.1.9 PACKAGE 9 D.2 Dataflow Model Concurrent Statements 10 D.2.1 Concurrent Signal Assignment 10 D.2.2 Conditional Signal Assignment 10 D.2.3 Selected Signal Assignment 11 D.2.4 Dataflow Model Sample 11 D.3 Behavioral Model Sequential Statements 12 D.3.1 PROCESS 12 D.3.2 Sequential Signal Assignment 12 D.3.3 Variable Assignment 12 D.3.4 WAIT 13 D.3.5 IF THEN ELSE 13 D.3.6 CASE 13 D.3.7 NULL 14 D.3.8 FOR 14 D.3.9 WHILE 14 D.3.10 LOOP 15 D.3.11 EXIT 15 D.3.12 NEXT 15 D.3.13 FUNCTION 15 D.3.14 PROCEDURE 16 D.3.15 Behavioral Model Sample 17 D.4 Structural Model Statements 17 D.4.1 COMPONENT Declaration 18 D.4.2 PORT MAP 18 D.4.3 OPEN 19 D.4.4 GENERATE 19 D.4.5 Structural Model Sample 19 D.5 Conversion Routines 21 D.5.1 CONV_INTEGER() 21 D.5.2 CONV_STD_LOGIC_VECTOR(,) 21