virtual signal

The virtual signal command creates a new signal, known only by the GUI (not the kernel), that consists of concatenations of signals and subelements as specified in <expressionString>. It cannot handle bit selects and slices of Verilog registers. Please see "Syntax and conventions" for more details on syntax.

Syntax

virtual signal

[-env <path>] [-install <path>] [-implicit] [-delay <time>] {<expressionString>} <name>

Arguments

-env <path>

Specifies a hierarchical context for the signal names in <expressionString>, so they don't all have to be full paths. Optional.

-install <path>

Causes the newly-created signal to become a child of the specified region. If install is not specified, the newly-created signal becomes a child of the nearest common ancestor of all objects appearing in <expressionString>. If the expression references more than one WLF file (dataset), the virtual signal will automatically be placed in region virtuals:/Signals. Optional.

-implicit

Used internally to create virtuals that are automatically saved with the List or Wave format. Optional.

-delay <time>

Specifies a value by which the virtual signal will be delayed. Optional. You can use negative values to look forward in time. If units are specified, the <time> option must be enclosed in curly braces. See the examples below for more details.

{<expressionString>}

A text string expression in the MTI GUI expression format that defines the signal and subelement concatenation. Can also be a literal constant or computed subexpression. Required. For details on syntax, please see "Syntax and conventions" .

<name>

The name you define for the virtual signal. Required. Case is ignored unless installed in a Verilog region. Use alpha, numeric, and underscore characters only, unless you are using VHDL extended identifier notation. If using VHDL extended identifier notation, <name> needs to be quoted with double quotes or with curly braces.

Examples

virtual signal -env sim:/chip/alu { (concat_range (4 downto 0))(a_04 & a_03 & a_02 & a_01 & a_00) } a

This command reconstructs a bus "sim:/chip/alu/a(4 downto 0)", using VHDL notation, assuming that a_ii are scalars all of the same type.

virtual signal -env sim:chip.alu { (concat_range [4:0])&{a_04, a_03, a_02, a_01, a_00} } a

This command reconstructs a bus "sim:chip.alu.a[4:0]", using Verilog notation. Note that the concatenation notation starts with "&{" rather than "{".

virtual signal -install sim:/testbench { /chipa/alu/a(19 downto 13) &
/chipa/decode/inst & /chipa/mode } stuff

Assuming /chipa/mode is of type integer and /chipa/alu/a is of type std_logic_vector, and /chipa/decode/inst is a user-defined enumeration, this example creates a signal sim:/testbench/stuff which is a record type with three fields corresponding to the three specified signals.

virtual signal -delay {10 ps} {/top/signalA} myDelayedSignalA

This command creates a virtual signal that is the same as /top/signalA except it is delayed by ten picoseconds.

virtual signal { chip.instruction[23:21] } address_mode

This command creates a three-bit signal, chip.address_mode, as an alias to the specified bits.

virtual signal {a & b & c & 3'b000} myextendedbus

This command concatenates signals a, b, and c with the literal constant '000'.

virtual signal {num & "000"} fullbus
add wave -unsigned fullbus

This command sequence adds three missing bits to the bus "num", creates a virtual signal named "fullbus", and then adds that signal to the wave window.

virtual signal { num31 & num30 & num29 & ... & num4 & num3 & "000" } fullbus
add wave -unsigned fullbus

This command sequence is used to reconstruct a bus that was fragmented by synthesis and is missing the lower three bits. Note that you would have to type in the actual bit names (i.e. num28, num27, etc.) represented by the ... in the syntax above.

virtual signal {(aold == anew) & (bold == bnew)} myequalityvector

This command creates a two-bit signal (with an enumerated type) based on the results of the subexpressions. For example, if aold equals anew, then the first bit is true (1). Alternatively, if bold does not equal bnew, the second bit is false (0). Each subexpression is evaluated independently.

Commands fully compatible with virtual signals

add list	add log / log	add wave
checkpoint and restore	delete	describe ("virtual describe" is a little faster)
down / up	examine	find
force/noforce	restart	left / right
search	searchlog	show

Commands compatible with virtual signals using [virtual expand <signal>]

check contention add	check contention config	check contention off
check float add	check float config	check float off
check stable on	check stable off	drivers
power add	power report	power reset
toggle add	toggle reset	toggle report
vcd add

Commands not currently compatible with virtual signals

when

See also

virtual count	virtual define	virtual delete
virtual describe	virtual expand	virtual function
virtual hide	virtual log	virtual nohide
virtual nolog	virtual region	virtual save
virtual show	virtual type	Virtual Objects (User-defined buses, and more)

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