Figure 4.1: Block Diagram of Rocky
The purpose of the Interface Subsystem (Rocky) is to latch all of the bus and CPU signals of interest into the 64 bit wide register for transmission across the ribbon cable, and to negotiate a system stall when requested by Bullwinkle. The software which works with Rocky is staller, which installs an interrupt handler and allows normal applications to be run on the machine.
The signals available on the PC backplane connectors that are recorded are the address lines A0-A23 and data lines D0-D15. Another 16 bits that are recorded come from a 16 bit counter circuit constructed using four 4-bit 74LS169A counter chips.
The counter can be incremented and cleared on certain events by programming the appropriate logic equation in the GAL isyspld. For initial testing purposes, the counter is incremented on each valid memory reference that is recorded, so that Bullwinkle can check that it records each set of data. In practice it would be more informative to have the counter increment each clock cycle and reset after each memory reference, to provide a measure of time between references. This modification can be made by simply reprogramming the GAL.
The remaining 8 lines available on the data path are available for connection to CPU signals that may or may not be brought out to the backplane connector. For example, wires could be connected to a socket of the CPU to record signals such as Code/Data access or CPU mode bits.
The 64-bit wide register is implemented as eight 8-bit 74LS273 register chips. Each chip has a common clock, which allows the data bits to be latched into the register at a different point in the bus cycle than the address, counter, and so on. The trigger pulses are defined by logic equations in the GAL, and so are easily changed. The only drawback is that all 8 auxiliary (CPU) inputs must be clocked at the same time.
Rocky is equipped with an 8-bit digital comparator for the purposes of decoding the I/O port address. Address lines A8, A7, A6, and A5 are compared with DIP switch settings, while A9 must be 1 and A4, A3, A2, and A1 must be 0. This allows the port address to be selected from among hex values 200, 220, 240, ..., 3E0. Rocky actually uses two addresses, for example, 300 and 301. Assume for purposes of discussion that the selected address base is 300 hex. Four additional DIP switch positions are used to select which IRQ line of the PC Rocky uses to interrupt the processor. Choices are IRQ2, IRQ3, IRQ6, IRQ7.
I/O port reads and writes on the PC take the form of IN port and OUT port, val. Rocky interprets OUT 300,X as a command to stop recording. The command to start recording is OUT 301,X. When recording is stopped, the REC signal stays constant, and the value of the GAL signal RUN is 0. Otherwise, RUN=1 and the REC signal goes high with each memory reference that is to be recorded. When an IN 300 operation is performed, Rocky places on the bus a register containing the values of SRQ, SACK, IRQ, and RUN.
Figure 4.2: Timing Diagram for Rocky
The handshaking and stall control works as follows. Rocky is in RUN mode, transmitting every memory reference to Bullwinkle. When Bullwinkle reaches its high-water mark, it raises SRQ. Immediately, Rocky raises an IRQ line to the SUT. Assuming the staller program has been run to install the interrupt handler, the IRQ causes the CPU to jump to the interrupt handler code. The interrupt handler performs an OUT 300,X, causing the RUN signal to go to 0. (Note IRQ returns to 0 at this point also.) Rocky raises the SACK signal to Bullwinkle, which takes that as an assurance that no further REC signals will be sent and consequently dumps its buffer contents to disk. Upon completion, Bullwinkle lowers SRQ. (SACK goes low at this point as a result.)
The interrupt handler has all this time been looping and doing an IN 300, checking the value of SRQ, effectively stalling whatever process was originally running on the SUT. Now that SRQ goes low, the interrupt handler performs an OUT 301,X and returns control to the main program. Rocky responds to the OUT 301,X by setting RUN to 1 and resuming transmission of REC pulses. So we're back to where we started.
For details see the GAL program isyspld.abl (Appendix E.2) and the interrupt handler code in staller.c (Appendix D.2).