The address counter hardware was tested in a 4.77 MHz 8086 system. Counts averaged around 50000 per clock tick, or 900 kc/s. This works out to roughly one memory reference for every 5 clock cycles. We'll call this a bus activity of 20%, a statistic which should be constant for all 8086 machines regardless of clock speed. However, the bus activity is highly dependent on the sequence of instructions being executed. Also, processors such as the 80286, 80386, and i486 perform each instruction in fewer clock cycles, so code fetches are done relatively more frequently, so the bus activity will be close to 50%. Since bus cycles require two clock cycles, 50% is the maximum. Further experimentation should be done to establish the effects of enabling/disabling the internal cache of the i486 as well. Only cache misses will show up on the address counter.