module isyspld
title 'Interface Subsystem PLD S. Harrington Spring 94'
isyspld device 'P22V10';
"Inputs
CLK, ALE, AEN pin 1,2,3;
IOR, IOW pin 4,5;
MEMR, MEMW pin 6,7;
!SEL pin 8; "from port address decoder
SRQ pin 9; "Stall ReQuest from RSYS
A0 pin 10;
"Outputs
EN244 pin 23; "active low enable for 244 to data bus
!IRQ pin 22; "active low IRq to PC (thru inverting buffer)
!Td,!Ta pin 21,20; "triggers for data/addr latches, inverted by 7414
REC pin 19; "active high Record strobe to RSYS
Running pin 18; "1 if in running state
Stalling pin 17; "1 if in stalling state
SACK pin 16; "active high SRQ Acknowledge to RSYS
CLoad pin 15; "active low Counter Preset
!CPulse pin 14; "rising edge triggers count/clear
PortWrite = SEL & !IOW & !AEN;
PortRead = SEL & !IOR & !AEN;
Equations "!=NOT &=AND #=Or $=XOR !$=XNOR
"REC goes high only during bus cycles that should be recorded.
"Note that at the Recording end, REC follows a path through a PLD
"which is longer than the path of the 64 bits of info. Make sure
"that the info will be stable for TP_REC since REC's rising edge
"latches the information into the FPGAs.
REC = !(Running & !AEN & (!MEMR # !MEMW));
"nREC.ar = ALE;
"nREC := nREC # (Running & !AEN & (!MEMR # !MEMW));
"nREC.clk = CLK;
"Trigger pulses occur on any bus cycle whether recorded or not.
" Tp = !CLK;
Td = MEMR & MEMW; "rising edge coincides with MR or MW rising
Ta = !ALE;
" Tc = ALE;
"CPulse and CLoad are coupled to 169-based counter circuit.
"The counter can be configured by making changes here
"to increment on different events. The current count is recorded
"alongside the address and data lines for each memory access.
"Make sure a CPulse happens while CLoad is low.
"For testing purposes, the counter should increment with each
"transmitted memory reference so we can tell if every set of data
"makes it to its destination.
"For practical purposes the counter may record CPU clock cycles
"between memory references for timing statistics.
CLoad = !(PortWrite & A0); "OUT P+1 resets count to 0
CPulse = !REC # (!CLK & !CLoad);
"IN P reads status of ISYS, such as SRQ and Running
EN244 = !PortRead;
"Running flag is turned off by an OUT P, on by OUT P+1
Stalling = !(A0 & PortWrite # Running);
Running = !(!A0 & PortWrite # Stalling);
"IRQ goes high on SRQ, low when cleared by OUT P
IRQ.c = CLK;
IRQ := Running & SRQ;
"SACK goes high on OUT P, low when SRQ is dropped.
"When high, the RSYS dumps SRAM to disk, then lowers SRQ.
SACK.c = CLK;
SACK := !Running & SRQ;
end isyspld