E.3 addrcomp.abl

module addrcomp
title 'Bullwinkle IO Port Address Comparator   S. Harrington   Fall 94'
addrcomp device 'P22V10';

"Inputs
    BCLK        pin 1;      "only needed for synching SRQ
    IOR         pin 2;
    IOW         pin 3;
    AEN         pin 4;
    SA4         pin 5;      "PC Bus address lines
    SA5         pin 6;
    SA6         pin 7;
    SA7         pin 8;
    SA8         pin 9;
    SA9         pin 10;
    SW5         pin 23;     "from DIP switch
    SW6         pin 22;
    SW7         pin 21;
    SW8         pin 20;
    AlmostFull  pin 13;     "active low from FPGAs

"Outputs
    PortSel     pin 18;
    STAT_EN     pin 17;     "active low enable for 244 to PC bus
    PortWrite   pin 16;     "IOW with A9:A4 = 0b1SSSS0XXXX (S=SW3:0 inputs)
    SRQ         pin 14;

"Macros
    SA = [SA9,SA8,SA7,SA6,SA5,SA4];
    SW = [SW8,SW7,SW6,SW5];

Equations "!=NOT &=AND #=Or $=XOR !$=XNOR


"IO Port Read or Write detected (combinational)
    PortSel = SA9 & (SA8!$SW8) & (SA7!$SW7) & (SA6!$SW6) & (SA5!$SW5) & !SA4;
    STAT_EN = !(PortSel & !IOR & !AEN);
    PortWrite = PortSel & !IOW & !AEN;

"Stall negotiation logic (clocked)
    SRQ := !AlmostFull;
    SRQ.C = BCLK;

test_vectors (
    [IOR,IOW,AEN,SA,SW] -> [PortSel,STAT_EN,PortWrite]
    )
"IOR IOW AEN    SA       SW     ->  Sel !Rd  Wr
[ 1,  1,  1, ^b101000, ^b0100 ] -> [ 1,  1,  0 ];
[ 0,  1,  0, ^b101000, ^b0100 ] -> [ 1,  0,  0 ];
[ 1,  0,  0, ^b101000, ^b0100 ] -> [ 1,  1,  1 ];
[ 1,  0,  0, ^b111000, ^b0100 ] -> [ 0,  1,  0 ];
[ 1,  0,  0, ^b111000, ^b1100 ] -> [ 1,  1,  1 ];
[ 1,  0,  1, ^b111000, ^b1100 ] -> [ 1,  1,  0 ];

test_vectors (
    [BCLK,AlmostFull] -> [SRQ]
    )
[.C., 1] -> [0];
[.C., 0] -> [1];

end addrcomp