E.4 iodecode.abl

module iodecode
title 'Bullwinkle PC I/O Decoder GAL   S. Harrington   Fall 94'
iodecode device 'P22V10';

"Inputs
    PCLK        pin 1;
    SA0         pin 2;
    SA1         pin 3;
    SA2         pin 4;
    SA3         pin 5;
    PortWrite   pin 6;

"Outputs
    Sel3        pin 23;     "module 3 Select
    Sel2        pin 22;     "module 2 Select
    Sel1        pin 21;     "module 1 Select
    Sel0        pin 20;     "module 0 Select
    Source      pin 19;     "0=remote, 1=local
    PageA16     pin 18;     "0=D0000, 1=E0000
    StartConfig pin 17;     "Active high reprogram signal to FPGAs
    StartWrite  pin 16;     "other stimuli for state machine changes
    StartRead   pin 15;
    GlobalReset pin 14;     "reset all CLBs and IOBs in FPGA

"Port Interface Logic
"Interface Specification summary:
"OUT P+0000 jumps into config mode
"OUT P+0010 jumps into either Acquire or HostWrite mode
"OUT P+0011 jumps into HostRead mode
"OUT P+010x sets Source to x (0=remote, 1=local)
"OUT P+011x sets PageA16 to x (0=E0000, 1=D0000)
"OUT P+10xy enables only module given by xy
"OUT P+110x sets all select signals to x
"OUT P+1111 pulses global reset line

"Macros
    SetValue = PortWrite & !SA3 & SA2;
    SelectAllMod = PortWrite & SA3 & SA2;
    SelectMod = PortWrite & SA3 & !SA2;
    SA = [SA3,SA2,SA1,SA0];
    Sel = [Sel3,Sel2,Sel1,Sel0];
    Mod = [SA1&SA0,SA1&!SA0,!SA1&SA0,!SA1&!SA0];
    X = .X.;

Equations "!=NOT &=AND #=Or $=XOR !$=XNOR

    StartRead = PortWrite & !SA3 & !SA2 & SA1 & SA0;
    StartWrite = PortWrite & !SA3 & !SA2 & SA1 & !SA0;
    StartConfig = PortWrite & !SA3 & !SA2 & !SA1 & !SA0;
    GlobalReset = PortWrite & SA3 & SA2 & SA1 & SA0;

    Source := ((SetValue & !SA1) & SA0) #
              (!(SetValue & !SA1) & Source);
    Source.C = PCLK;

    PageA16 := ((SetValue & SA1) & SA0) #
              (!(SetValue & SA1) & PageA16);
    PageA16.C = PCLK;
    
    Sel := (SelectAllMod & SA0)
            # (SelectMod & Mod)
            # (!SelectAllMod & !SelectMod & Sel.FB);
    Sel.C = PCLK;

test_vectors (
    [PCLK,SA,PortWrite] ->
    [Sel,Source,PageA16,StartConfig,StartWrite,StartRead,GlobalReset]
    )
[ X ,    X  , 0 ] -> [    X  , X, X, 0, 0, 0, 0 ];
[.C., ^b0101, 1 ] -> [    X  , 1, X, 0, 0, 0, 0 ];
[.C., ^b0111, 1 ] -> [    X  , 1, 1, 0, 0, 0, 0 ];
[.C., ^b0100, 1 ] -> [    X  , 0, 1, 0, 0, 0, 0 ];
[.C., ^b0110, 1 ] -> [    X  , 0, 0, 0, 0, 0, 0 ];
[.C., ^b1000, 1 ] -> [ ^b0001, 0, 0, 0, 0, 0, 0 ];
[.C., ^b1001, 1 ] -> [ ^b0010, 0, 0, 0, 0, 0, 0 ];
[.C., ^b1010, 1 ] -> [ ^b0100, 0, 0, 0, 0, 0, 0 ];
[.C., ^b1011, 1 ] -> [ ^b1000, 0, 0, 0, 0, 0, 0 ];
[.C., ^b1101, 1 ] -> [ ^b1111, 0, 0, 0, 0, 0, 0 ];
[.C., ^b0000, 1 ] -> [ ^b1111, 0, 0, 1, 0, 0, 0 ];
[.C., ^b0010, 1 ] -> [ ^b1111, 0, 0, 0, 1, 0, 0 ];
[.C., ^b0011, 1 ] -> [ ^b1111, 0, 0, 0, 0, 1, 0 ];
[.C., ^b1111, 1 ] -> [ ^b1111, 0, 0, 0, 0, 0, 1 ];
[.C.,    X  , 0 ] -> [ ^b1111, 0, 0, 0, 0, 0, 0 ];

end iodecode