E.5 bstate.abl

module bstate
title 'Bullwinkle Bus Interface Decoder GAL   S. Harrington   Fall 94'
bstate device 'P22V10';

"Inputs
    BCLK        pin 1;
    SACK        pin 2;      "Stall Acknowledge from Rocky
    Source      pin 3;
    StartConfig pin 4;
    StartWrite  pin 5;
    StartRead   pin 6;
    Sel3        pin 8;
    Sel2        pin 9;
    Sel1        pin 10;
    Sel0        pin 11;
    Full        pin 13;     "wired-OR of F signals from FPGAs active low

"Outputs
    BBX_DIR     pin 23;     "Bullwinkle Bus Transceiver
    LBX3_EN     pin 22;     "Local Bus Transceiver 3 active low enable
    LBX2_EN     pin 21;     "Local Bus Transceiver 2
    LBX1_EN     pin 20;     "Local Bus Transceiver 1
    LBX0_EN     pin 19;     "Local Bus Transceiver 0
    DAR_EN      pin 18;     "Data Acquisition Register active high enable
    Q1          pin 17 istype 'reg,buffer';     "State variables
    Q0          pin 16 istype 'reg,buffer';
    Extract     pin 15;     "Active low control pin to FPGAs
    Program     pin 14;     "active-high reprogram signal to FPGAs

"State Assignments
    StateReg = [Q1,Q0];
    ConfigS     = [0,0];
    AcquireS    = [0,1];
    HostWriteS  = [1,0];
    HostReadS   = [1,1];

    Acquire = !Q1.FB & Q0.FB;
    Config = !Q1.FB & !Q0.FB;
    HostWrite = Q1.FB & !Q0.FB;
    HostRead = Q1.FB & Q0.FB;

    Sel = [Sel3,Sel2,Sel1,Sel0];
    LBX_EN = [LBX3_EN,LBX2_EN,LBX1_EN,LBX0_EN];
    Ck = .C.;
    X = .X.;

Equations "!=NOT &=AND #=Or $=XOR !$=XNOR

    [Q1,Q0].C = BCLK;

    "Both of these signals are inverted by a 74LS14
    "to improve fanout to the 4 FPGAs.
    Extract = !HostRead;
    Program = Config;

    "Data Acquisition Registers (four in lock-step)
    DAR_EN = Acquire;

    "Bullwinkle Bus Transceiver
    "DIR 0=fromHost,1=toHost
    BBX_DIR = HostRead; "write values to PC bus only in HostRead mode

    "Local Bus Transceivers (one per buffer module)
    "DIR 0=toHost,1=fromHost
    "LBX_DIR = Q0
    "LBX_DIR = Acquire # HostRead;
    LBX_EN = !(Config #
            HostWrite #
            (HostRead & Sel));

state_diagram StateReg
    "Note that Full is active low
    state ConfigS:
        if (StartConfig) then ConfigS
        else if (StartWrite & !Source) then AcquireS
        else if (StartWrite & Source) then HostWriteS
        else ConfigS;
    state AcquireS:
        if (StartConfig) then ConfigS
        else if (StartRead # SACK # !Full) then HostReadS
        else if (StartWrite & Source) then HostWriteS
        else AcquireS;
    state HostWriteS:
        if (StartConfig) then ConfigS
        else if (StartRead # !Full) then HostReadS
        else if (StartWrite & !Source) then AcquireS
        else HostWriteS;
    state HostReadS:
        if (StartConfig) then ConfigS
        else if (StartWrite & !Source) then AcquireS
        else if (StartWrite & Source) then HostWriteS
        else HostReadS;

test_vectors (
    [BCLK,Full,SACK,Source,StartConfig,StartWrite,StartRead,Sel] ->
    [Q1,Q0,DAR_EN,BBX_DIR,LBX_EN,Extract,Program]
    )
"Enter configuration state (0,0)
[Ck,X,X,X,1,X,X,   X  ] -> [0,0,0,0,^b0000,1,1];
[Ck,X,X,X,0,0,0,   X  ] -> [0,0,0,0,^b0000,1,1];
[Ck,1,0,0,0,0,0,   X  ] -> [0,0,0,0,^b0000,1,1];
"StartWrite (port write) signifies config done, go to Acquire state (0,1)
[Ck,1,0,0,0,1,0,   X  ] -> [0,1,1,0,^b1111,1,0];
[Ck,1,0,0,0,0,0,   X  ] -> [0,1,1,0,^b1111,1,0];
"SACK signal puts us in HostRead state (1,1)
[Ck,1,1,0,0,0,0,^b0001] -> [1,1,0,1,^b1110,0,0];
[Ck,1,0,0,0,0,0,^b0010] -> [1,1,0,1,^b1101,0,0];
[Ck,1,0,0,0,0,0,^b0100] -> [1,1,0,1,^b1011,0,0];
[Ck,1,0,0,0,0,0,^b1000] -> [1,1,0,1,^b0111,0,0];
"Issue StartWrite command through io port, from host this time
[Ck,1,0,1,0,1,0,   X  ] -> [1,0,0,0,^b0000,1,0];
"Full signal puts us back in HostRead state
[Ck,0,0,1,0,0,0,^b1000] -> [1,1,0,1,^b0111,0,0];

end bstate