module btrigger
title 'Bullwinkle Bus Interface Decoder GAL S. Harrington Fall 94'
btrigger device 'P22V10';
"Inputs
BCLK pin 1;
SA16 pin 2;
SA17 pin 3;
SA18 pin 4;
SA19 pin 5;
MEMR pin 6;
MEMW pin 7;
PageA16 pin 8; "also affects A17 select: hi=D000,lo=E000
REC pin 9;
Q0 pin 10;
Q1 pin 11;
"Outputs
BBX_EN pin 23; "Bullwinkle Bus Transceiver active low enable
CCLK pin 22; "FPGA Configuration pulse active low
DAR_CLK0 pin 21; "(synchronized to BCLK)
DAR_CLK1 pin 20; "same as DAR_CLK, duplicated for fanout
DAR_CLK2 pin 19; "same as DAR_CLK, duplicated for fanout
DAR_CLK3 pin 18; "same as DAR_CLK, duplicated for fanout
Trigger0 pin 17; "synchronized trigger to FPGAs active high
Trigger1 pin 16; "same as Trigger, duplicated for fanout
MemRW pin 15; "true during either MemWrite or MemRead
MemCS16 pin 14; "0 when MemRW=1, HiZ otherwise
"Macros
PageSel = (PageA16 & (SA19 & SA18 & !SA17 & SA16)) #
(!PageA16 & (SA19 & SA18 & SA17 & !SA16));
MemWrite = PageSel & !MEMW;
MemRead = PageSel & !MEMR;
Config = !Q1 & !Q0;
Acquire = !Q1 & Q0;
HostWrite = Q1 & !Q0;
HostRead = Q1 & Q0;
SAhi = [SA19,SA18,SA17,SA16];
Ck = .C.;
X = .X.;
Z = .Z.;
Equations "!=NOT &=AND #=Or $=XOR !$=XNOR
"Assert a 0 on MemCS16 only during MemWrite or Read
MemRW = MemWrite # MemRead;
MemCS16 = 0;
MemCS16.OE = MemRW;
"Cclk is normally high, but goes low briefly during config bit
"writes. When it returns to 1, the bus data (DIN) should have
"been valid at the FPGA for 60 ns. See Leibson p.66 and Xilinx
"data book p.2-125.
"t(CCLK LH at FPGA pin) = tPLH(74LS14) + t(CCLK HL at GAL pin)
"t(CCLK HL at GAL pin) = tPG + min{t(address invalid), t(MEMW HL)}
"t(address invalid) = t0 + 1.5*T(PCLK)
"t(MEMW LH) = t0 + 2*T(PCLK) (MEMW going inactive)
"t(DIN valid at FPGA) = tP(LBX 74HCTLS245) + tP(BBX 74HCTLS245)
" + t(D0 valid on system bus)
"t(D0 valid) = t0 + T(PCLK)
"t(DIN not valid at FPGA) = tP(LBX 74HCTLS245) + tP(BBX 74HCTLS245)
" + t(D0 not valid on system bus)
"t(D0 not valid) = t0 + 2*T(PCLK) + epsilon
"We require t(DCC) = t(CCLK LH) - t(DIN valid) >= 60 ns
"and t(CCD) = t(DIN not valid) - t(CCLK LH) >= 0
"assume tP(74HCTLS245) = 15 ns, tP(74LS14) = 15 ns, tPG = 25 ns.
"t(DCC) = 15 + 25 + 1.5*T(PCLK) + t0 - 15 - 15 - T(PCLK) - t0
" = 10 + T(PCLK)/2 >= 60 ns
"so T(PCLK) >= 100 ns, or f <= 10 MHz.
"t(CCD) = 15 + 15 + t0 + 2*T(PCLK) + epsilon - 15 - 25 - t0 - 1.5*T(PCLK)
" = T(PCLK)/2 + epsilon - 10 >= 0
"so T(PCLK) >= 20 ns
CCLK = !( (Config & !MemWrite) #
Acquire #
HostWrite #
HostRead );
"FPGA Trigger input
"Note that BCLK must be faster than the host system bus rate
"so that the data put to the FGPAs during a MemWrite is still
"around when the trigger pulse (synchro with BCLK) happens.
"The trigger during HostRead mode causes the FPGA to update pointers
"and put the _next_ value on the output bus. It should therefore
"not happen until the host PC has completed the read of the last
"value. That is why we raise Trigger on MemRead falling.
Trigger0 := (Acquire & REC) #
(HostWrite & MemWrite) #
(HostRead & !MemRead);
Trigger0.C = BCLK;
Trigger1 := (Acquire & REC) #
(HostWrite & MemWrite) #
(HostRead & !MemRead);
Trigger1.C = BCLK;
"Data Acquisition Registers (four in lock-step)
"While DAR_CLK is hi, the register should hold its value stable.
DAR_CLK0 := REC;
DAR_CLK1 := REC;
DAR_CLK2 := REC;
DAR_CLK3 := REC;
DAR_CLK0.C = BCLK;
DAR_CLK1.C = BCLK;
DAR_CLK2.C = BCLK;
DAR_CLK3.C = BCLK;
"Bullwinkle Bus Transceiver
BBX_EN = !(Config #
HostWrite #
(HostRead & MemRead));
test_vectors (
[BCLK,SAhi,PageA16,MEMW,MEMR,REC,Q1,Q0] ->
[CCLK,BBX_EN,DAR_CLK0,Trigger0,MemCS16]
)
"In config mode
[Ck,^b1110,0,1,1,0,0,0] -> [0,0,0,0,Z];
[ 0,^b1110,0,1,1,0,0,0] -> [0,0,0,0,Z];
[ 0,^b1110,0,0,1,0,0,0] -> [1,0,0,0,0];
[ 0,^b1101,0,0,1,0,0,0] -> [0,0,0,0,Z];
"In acquire mode
[Ck, X ,X,1,1,0,0,1] -> [0,1,0,0,Z];
[Ck, X ,X,1,1,1,0,1] -> [0,1,1,1,Z];
[Ck, X ,X,1,1,0,0,1] -> [0,1,0,0,Z];
"In hostread mode
"Note how when we first enter hostread mode the fpga gets a trigger
[Ck,^b1101,1,1,1,0,1,1] -> [0,1,0,1,Z];
"perform a memread - BBX is enabled
[Ck,^b1101,1,1,0,0,1,1] -> [0,0,0,0,0];
"trigger goes high after memread is complete
[Ck,^b1101,1,1,1,0,1,1] -> [0,1,0,1,Z];
end btrigger