![]() |
The Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is a high-level, modular language that is completely integrated into the Quartus® II system. You can use the Quartus II Text Editor or another text editor to create VHDL Design Files (.vhd). You can then create entire hierarchical projects with VHDL, or mix VHDL Design Files with other types of design files in a hierarchical project.
VHDL Design Files can contain any combination of Quartus II-supported constructs. They can also contain Altera-provided logic functions, including primitives and megafunctions, and user-defined logic functions. In the Text Editor, you can create a Block Symbol File (.bsf) that represents a VHDL Design File and incorporate it into a Block Design File (.bdf). Similarly, you can create an AHDL Include File (.inc) that represents a VHDL Design File and incorporate it into a Text Design File (.tdf) or Verilog Design File (.v).
Although you can use any ASCII text editor to create VHDL designs, the Quartus II Text Editor allows you to take advantage of features available only in the Quartus II software, including VHDL templates, syntax coloring, and error location.
The Compiler allows you to check the syntax of a VHDL design quickly with the Analyze Current File command (Processing menu). You can use the Quartus II Messages window or the Messages section of the Report window to locate errors in a VHDL Design File and highlight them in the Text Editor. You can also create VHDL Output Files (.vho) or Standard Delay Format (SDF) Output Files (.sdo) for use with simulation tools from other EDA vendors.
![]() |
|
- PLDWorld - |
|
Created by chm2web html help conversion utility. |