See Also

The Verilog Hardware Description Language is a high-level, modular language that is completely integrated into the Quartus^® II system. You can use the Quartus II Text Editor or another text editor to create Verilog Design Files (.v). You can then create entire hierarchical projects with Verilog HDL, or mix Verilog Design Files with other types of design files in a hierarchical project.

Verilog Design Files can contain any combination of Quartus^®-supported constructs. They can also contain Altera-provided logic functions, including primitives and megafunctions, and user-defined logic functions. In the Text Editor, you can create a Block Symbol File (.bsf) that represents a Verilog Design File and incorporate it into a Block Design File (.bdf). Similarly, you can create an AHDL Include File (.inc) that represents a Verilog Design File and incorporate it into an AHDL Text Design File (.tdf) or another Verilog Design File.

Although you can use any ASCII text editor to create Verilog HDL designs, the Quartus II Text Editor allows you to take advantage of features available only in the Quartus II software, including Verilog HDL templates, syntax coloring, and error location.

The Compiler allows you to check the syntax of a Verilog HDL design quickly with the Analyze Current File command (Processing menu). You can identify and locate errors in a Verilog Design File with the Quartus II Messages window or the Messages section of the Report window You can also create Verilog HDL Output Files (.vo) or Standard Delay Format (SDF) Output Files (.sdo) for use with simulation tools from other EDA vendors.

The Quartus II software supports a subset of the constructs defined by the IEEE Std 1364-1995 and IEEE Std 1364-2001. For details about the level of Quartus II support for each construct, see Quartus II Verilog HDL Support and Quartus II Support for Verilog 2001.

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