General FPGA Design Information
Introduction to Actel FPGA Architecture
Designing with FPGAs Compared with SSI/MSI Devices
Designing with FPGAs Compared with PLD Devices
FPGA Design for ASIC-Experienced Designers
Comparing FPGA Solutions
Estimating Performance and Capacity of Actel Devices
Predicting the Power Dissipation of Actel FPGAs
Board Level Considerations for Actel FPGAs
Simultaneously Switching Output Limits for Actel FPGAs
Designing for Migration to Actel MPGAs
Using Silicon Explorer with SX FPGAs
Two-Way Mixed Voltage Interfacing of Actel's FPGAs
Integrating Multiple CPLD Functions in an Actel SX Device
3200DX Dual-Port Random Access Memory (RAM)
3200DX Wide Decode Modules
IEEE Standard 1149.1 (JTAG) in the 3200DX Family
3200DX Quadrant Clocks
Fast On and Off Chip Delays with 1200XL and 3200DX I/O Latches
Using ACT 3 Family I/O Macros
Global Clock Networks
Verifying Setup and Hold Times in Timing Tools
Power-Up Design Considerations
High-Level Design Benchmark Report
Timing Analysis: The Key to High Performance System Logic Design
Using Silicon Explorer to Debug the 100 Mbit Ethernet Dual-Port Bridge
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