Gateway Area

GATEWAY to design excellence

This is a growing page ... it provides links to pages used by GateWay students ... and occasional instructions relating to the lab.

Gateway Laboratory introduction
A quick introduction to synchronous design
A more detailed introduction to synchronous design
Verilog design style for synchronous design
VERILOG RESOURCE AREA

Training sessions for Autumn 1997

SESSION ONE

SESSION TWO

SESSION THREE

Christmas ASSIGNMENT

Feedback on the Christmas assignment

Design exercise for Spring 1998

... is HERE

Writing for Gateway

GATEWAY report format

Examples of Electronics Letters to illustrate report format:

Feedback from 1996 showing common mistakes

General tips on writing skills

Design task example - from Spring 1997

The exercise specification
An example solution can be found here - illustrating both bit-slice techniques and the use of setup and hold parameters.
A possible electronics letter

Student feedback on learning laboratory (1996-7)

Local links ...

... to other articles on VLSI design and Professional Skills

ACKNOWLEDGEMENTS

A special thanks goes to Cadence UK for donating a loan of multiple licences to create the Cadence Laboratory for Scotland at the Department of Electrical Engineering in the University of Edinburgh, Scotland, UK

Gerard M Blair was a Senior Lecturer in VLSI Design and Project Management in the Department of Electrical Engineering, The University of Edinburgh, Scotland UK. He welcomes feedback either by email gerard@ee.ed.ac.uk or by other methods found here