GATEWAY LABORATORY: SESSION ONE
Objectives
The objectives of this session are:
-
to explore the on-line material
-
to learn to use the Verilog editor
-
to run (and debug) simple Verilog programs
Explore on-line manual
In the Netscape window where you are reading this, you can create a
second window so that you can read these instructions and
explore the web pages at the same time.
-
point with the cursor at the Netscape window and
while holding down the "alt" key (a little left of the space
bar) press the "n" key
A new window should appear. This can also be done using the "File"
entry in the menu bar and selecting a
New Web Browser.
In the new window, find you way back to the Gateway page - and
take a brief look at the sort of documents and links there
to get an idea of what resources are available.
Next, enter the
Verilog resource area
and do the same - and finally enter the
Verilog manual.
During this session and the following one, you should aim to read
through the manual and the examples contained within it. But for now,
let's learn the editor.
Xemacs editor for Verilog
The idea is to run through the on-line tutorial in the Xemacs editor.
This can be called by clicking on the
Gateway
icon in the top right of your screen.
To start the tutorial:
there is a menu item, under the
Help
menu bar,J called:
Xemacs tutorial.
Alternatively, point to the Xemacs window, hold down the "control" key and
type "h", release the control key and type "t".
Now - spend as long as necessary learning to use the editor.
NOTE:
previous students have suggested that ten minutes is enough to
learn the few basic commands and that the rest of the tutorial is
full of commands which are never used and/or are quickly forgotten.
So read and play for about twenty minutes and then come back to the
tutorial later if you feel that your editing skills are inadequate.
Running Verilog Programs
There are four buttons in the Xemacs editor
associated with the Verilog environment:
-
Verilog
- runs the code in the current window
-
Kill
- terminates a program which runs wild
-
Errors
- helps you find the errors by putting the pointer
to the relevant line
-
Reformat
- tries to align any highlighted text so that it
looks pretty (and is more readable).
The first thing we want to do is to pickup some text
form the Netscape window and put it into the Xemacs
window
- First:
-
Let us open a buffer/file in the
Xemacs window. Bring up the
File
menu bar and select the
Open
command.
In the bottom of the Xemacs window, there is a line starting
with
Find file;
as you type (pointing at the Xemacs window), the text
appears in that line. Type "hello.v" and then press the
Return
key. This is now our current file.
- Second:
-
Below these instructions, there is a small program.
Point to the start of it with your cursor and WHILE
HOLDING THE LEFT MOUSE BUTTON DOWN), drag the cursor to the
end of the program; release the mouse button but leave the
cursor pointing at the Netscape window.
Holding the
Alt
button down, type the letter
c.
We have now copied the
program into a local buffer. We can write this to the
Xemacs window by moving the cursor to point at that window
and pressing the
Paste
key which is located in that set of 10 keys at the left of your
keyboard.
- Third:
-
Using the mouse as in "First" above, highlight the program in
the Xemacs window - and then click the
Reformat
menu button. The code should jump to the correct format.
- Fourth:
-
Click on the
Verilog
menu button - and run the program. A second window will appear to
display the output
SAMPLE PROGRAM ONE
module sayHello;
initial $display("Hello");
endmodule
Notice that the Netscape and Xemacs windows use different
key strokes to achieve these operations of
copy
and
paste.
However, in both windows the operations can be found in the
Edit
menu bar. AND in Xemacs there are
menu buttons also.
IMPORTANT:
files of verilog code MUST end with a ".v" so that the editor knows to
do the highlighting properly.
Let us try something else - delete a ";" at the end of the first line -
and click on the
Verilog
button.
When the program has run (and the result says that there is an error)
click on the
Error
menu button and watch the two windows jump to indicate where the
error occurs. NOTE, missing out the ";" is the most common beginner's
error - and NOTE that the error check only notices the problem at
the beginning of the
next
line of text.
Now try to type this program in yourself - in the same Xemacs window
watching carefully
as the colours change and the returns and indentations are done for
you. Make sure you do a final
return
after the
endmodule
Delete the original program (highlight it with the mouse and press the
Cut
key) - and now run your version to see if there are any errors.
A Simple Practice
You now have the basic skills. In the Netscape window in which
you were exploring the on-line documentation, find the
"VERILOG INTRODUCTION" or "Verilog resource" page and look at
a small design example: an inverting multiplexor.
Copy and Paste this example into the Xemacs window and
use
File -> Save as
to store it in a new file. Run it to see if it works.
Read through the code to see if you can understand the basic
structure of the language -
the brave might like to enhance it as:
-
a 4-1 inverting multiplexor which takes in four 1-bit buses
(which will need two control signals)
It is important that you TRY this BEFORE looking at the
the answers which can be found
here .
First Design tasks
The objectives of this section are:
-
to create both behavioural and gate-level modules
-
to run simulations to test their function
You need to read the three documents:
-
A quick introduction to synchronous design
-
A more detailed introduction to synchronous design
-
Verilog design style for synchronous design
in the
GATEWAY to design excellence
home page before attempting the following activities.
Activity 1
Basic Dtypes
For each of the following, create the required module and perform
simulations which test its function.
-
a behavioural module of a positive edge-triggered one-bit dtype
(see the
bog-standard
Dtype in the third document mentioned above).
-
a 4-bit version (this involves making the
d
and
out
signals/variables into four-bit buses).
-
a behavioural module of a positive edge-triggered one-bit dtype
with a synchronous reset (active low) (see the third document mentioned above)
-
a gate-level module which combines a two-input boolean gate
with an instance of the first module you designed in this
activity [hint:
be careful of the "polarity" of the output]
Thus you will be wanting to define a new module which
instances (calls) a previously module and a gate:
module origMod ( <parameter list> );
...
endmodule
module newOne (out, clk, reset, d);
...
someGate (<list of inputs and outputs>)
origMod modName (<list of inputs and outputs>)
...
<something to invert the signal to get the right polarity>
...
endmodule
In fact this can be done using a
nand
gate and a
Dtype
with the output inverted - or -
using an
and
gate and a
Dtype
without a final inversion.
-
a behavioural module for an Enable flipflop with reset (i.e.
a dtype which is only updated if the control signal
enable
is high, but resets to zero when reset is
high
whatever the
value of enable) [the answer (well almost but not quite) is
in the third document recommended above]
-
an inverting multiplexor - in any style you choose - see
the small design example in the
VERILOG home page
-
a gate-level module of the Enable flipflop (calling a NOR, inv_mux and dtype -
if in doubt - read the
on-line manual:
Modules->Modules
)
-
a behavioural module of a Toggle flipflop (including a reset input)
whose description is given in the counter section of the second
document recommended above.
Activity 2
Shift Registers
Now we need to put the above modules together to form more interesting
functions - remember that you must write tests to check that you are right.
-
create gate-level shift-register which takes an input stream of
one-bit and delays it for three clock cycles (using calls
to one of the modules already defined - do not forget the
clock input).
-
create a behavioural version of the same perhaps using code which incudes
statements like this:
reg [2:0] regMem;
reg out
...
{out, regMem} = {regMem, in};
Note that the assignment to a register will need to be within an
always block (with what guard ?) and you will need to
check the manual on the concatenation operator
-
create a gate level description of a shift register which takes 4-bit
words and delays them for 3 clock cycles. Use instances
of the 4-bit dtype from the first activity.
-
To create a behavioural module for this is a little harder than
for a one-bit shift register. The following code will do it:
module shift(out, clk, in);
output [3:0] out;
input clk;
input [3:0] in;
reg [3:0] shiftMem [0:3];
assign out = shiftMem[3];
always @(posedge clk) begin
shiftMem[3] = shiftMem[2];
shiftMem[2] = shiftMem[1];
shiftMem[1] = shiftMem[0];
shiftMem[0] = in;
end
endmodule // shift
module testShift;
reg [3:0] a;
reg clk;
wire [3:0] out;
integer i;
shift mod1 (out, clk, a);
initial begin
clk = 0;
forever #5 clk = ~clk;
end // initial begin
initial #2 forever #10 $display("%d %d", a, out);
initial begin
i = 0;
repeat (9) begin
#10 a = i;
i = i + 1;
end // repeat (9)
#10 $finish;
end // initial begin
endmodule // testShift
Copy this code and change the
shift
module so that three of the assignments are performed within a
for
loop. Note that the order in which the assignments are
made is significant [get it wrong and you over-write a
register before it is read].
Now change the end condition of the
for
loop and the size of the
shiftMem
array to make a delay of 12 clock cycles. TEST IT.
Activity 3
Counters
The second document recommended above has a section on digital counter
design, and the
second large worked-example in the
on-line manual
is also about counters. It might be worth reading these
before writing the following code.
-
Create a gate-level 4-bit counter module
using several toggle flipflop (with a reset) and AND gates
[Remember to start with a reset in the test procedure]
-
Create a behavioural module which does the same but which uses
a simple 4-bit register which is incremented (do not forget the
reset)
-
For both of the above, create new modules which start at 4'b0010
rather than zero (you may need to design a second toggle flipflop)
-
Remembering to include a global reset, update
the behavioural module to be a counter which starts at 3 and finishes
at 12 (i.e. 3 4 5 6 7 8 9 10 11 12 3 4 5 6 ... ).