The spring term design exercise is really good. It was good example of hierarchical design of a digital circuit. It enabled me to put the skills I learned in 2nd year digital circuits into practice.
The end
Gaining a better understanding of digital design using a fairly interesting method involving prgramming.
getting the final design working
The help given by the attendants with the code and the design
The limitless variations that can be applied to the design process
Using Verilog has generally broadened my understanding of the use of functions in C. It was also nice to get a program finally doing something useful.
When things work!
i felt I finally got to grips with the digital design from second year. Verilog really helps you to see the overall picture. The demonstrators were very helpful.
The towers of hanoi design problem was by far the better and more enjoyable of the two main problems. The design and coding was much more enjoyable than first expected.
The emphasis on design.
I thought Verilog was a very smart way of implementing Digital logic design.
The Post-graduates help was very important in the early stages of the lab when learning the basics was important. Later on, they were again useful when the problems became more challenging.
can really allows us to demonstrate the design of digital circuits the exercises are really interesting
Got to design some not so 'useful' circuits, but it was fun and enjoyable.
Very competent helpers.
you were able to work at the lab at any time with out the need for a lab supervisor
Having availibility to the equipment outside labouratory hours.
final design when I understood how to implemented the code.
the spring design project was interesting and set at about the right level
The second design was quite enjoyable, as it allowed a certain amount of freedom and made you feel like you had achieved something.
The Verilog is used widely in industry for digital design.
assistant available
Able to work when required and in my own time.
The worst aspect of the lab was the way all the information is on the web. The first two sessions were really boring. I found it really difficult to motivate myself to read every thing. The tutorial on using the editor was a waste of time because it is so similar C. I only use 1 or 2 of those keystrokes.
The begining
None
it was hard to get help in the labs - the supervisors generally got monopolised by a few people. It is also quite hard to learn all the stuff off the internet, although I realise it is the only way to present all the information.
There were not enough labs
I didn't find anything that unenjoyable.
Electronics letters
Wading through the help pages on the editor was a waste of time. I cant say that i use/remember many of the short cut commands.
Wading through the pages and pages of the manuals in the first term in order to try to understand the language and operation of the emacs window.
The fact that all the notes are on the web make it hard to prepare outside the lab.
Perhaps the pace was a bit slow... I do not think that the project *really* warrants a whole term...
When the labs were busy, it was hard to get hold of the lab demonstartors.
Can't think of any.
It was scheduled for friday mornings.
trying to learn a new language from scratch with no teaching although this got easier as time went on
Lab techs always seemed too busy to offer much help.(Although their help was good)
First couple of sessions when I wasn't quite sure what was going on.
the first term exercises became boring appearing to have no use thus slowing the learing process
Confusing at the start of second design as I was unsure where to begin the design.
The pace of the lab changed rapidly after first 2 sessions in autumn term.
no assessment. like given a particular circuit, write a program that sort of stuff.
The on'line manual was difficult to use. Information was sparse. Certain commands were not explained which would have been useful. I find it difficult to read froma screen for any period of time. especially when the writing is small
An introductory lecture would be really useful. A lecture introducing the concept of a hardware description language and some of the basics. Simpler instructions on writing stimulus for circuits would be useful too.
A little more help on hand would have been good to gain a faster grasp of the work.
A few introductory lectures to introduce the basics of verilog would be helpful. At the start I found it very daunting, but I now realise verilog is quite easy to program. I also felt at the start that the programming was the hardest part, not the actual paper design.
Have more labs which run for two hours instead of three.
I would have more lab sessions but possibly for shorter time periods - say 2 hours instead of 3. More supervisors would be very advantageous since many people have sore arms due to holding them in the air for so long!!
Make the design exersise tougher, it simply dosen't compare with microway!
Time would be better spent in the first lab doing a more structured introductory design exercise. Verilog is very easy once you get to grips with the code.
Perhaps less time spent reading through the emacs manual as although it is helpful, the majority of the information is not necessary for the operation of verilog. This time could perhaps be spent on a simple demonstration on the principles of verilog coding.
Printed notes at least of the manual and a clearer explanation of the use of the commands 'reg' and where 'assign' should or shouldn't be used.
Perhaps a slightly more "application oriented" project. Though I enjoyed the "Towers of Hanoi" problem, it is not really one that we would want to rush out and market ;)
The "keywords" appendix in the manual could give a brief summary of what each command does rather than just listing them. Admittedly a large number of the commands are explained in the manual, however it was not always clear which sub-sections contained the infortmation that was required.
the time for the second project is a bit long actually five weeks will do cos we've got the christmas holiday to think about the design. Once we come back , we can then write our code.
More design projects, probably two instead of only one for the Spring term
Award some marks for the initial stages. It is the best way to ensure people le people do the work and teach themselves making the latter projects less daunting.
Some lectures that cover example programs
Teach good design practice for the structure and interlinking of modules and stimulus. (Eg.some programs appeared to have half the modules written into the stimulus)- How large should modules be? Is a lot of small modules better than one big one? etc. Emphasize freedom of design. A lot of students tend to think that the only way to get qood marks is to follow your design hints (Is this the case?)Eg.There is the general impression that you must use tri-state outputs for the spring design.
Maybe have some sort of talk/lecture at the beginning just as a introduction to explain the aims of the lab.
maybe, a few basic lectures to make people understand what they are learning and the basics of the design
Small lectures or tutorials to allow people who aren't sure where to start a few hints so they don't fall behind and become depressed. I'm sure the demonstrators were probably asked the same questions over and over again anyway.
The final design exercise should be more demanding.
In my opinon, I felt that the Autum assessment was unfair. Somebody can just take a design from somewhere, rewrite it beautiful and can probably get an "A" (I think). Personally, I spent time writing the code that works for the system described in the source paper. Someone else may not have done that. In fact, there are many who can't generate a proper code. The marks allocation should take this into account.
a couple of lectures, (similar to Computer Studies but not as many as that) so that the basics can be explained.
At first I couldn't be bothered teaching myself how to use verilog. But when I had to (ie spring term) I found I quite enjoyed being able to design a digital cicuit on paper then quickly simulate and test my design with verilog. I like the way the language is really modular, it helps me to understand my design bit by bit as it gets more complex.
The lab was quite enjoyable, but some more guidance along the way would be helpful. I only learned to program verilog 3 weeks ago. I couldn't do it for last term's exercise, because I thought it was too difficult.
The Median Filter was conceptually more difficult than the Hanoi puzzle but this might have been because it was the first design example.
Overall the lab was much better than first impressions suggested. Understanding the design for the median filter was much more difficult than the towers of hanoi problem. This may have been due to a greater understanding of the verilog program by the end of term 2, but I suspect the it is also because the median filter design is difficult to get to grips with.
None
A very enjoyable project indeed.
I particularly enjoyed using Verilog. I like the idea of modular programming (building up complex behaviour from simple sub-modules) and hope I will get the chance to use what I have learned next year.
It is a good lab module
More time should should have been given to learn the basics? For me (and others I'm sure) this was the first time using C-langauge let alone Verilog. Although the introductory lab sessions were excellently constructed, a couple of rushed sessions is hardly enough to set you up to implement good design programming from there on in.
The demonstrators were really helpful and the extra session in week 9 was definitely useful. I don't like communicating with people who are in the same building by Email and the Web but the amount of interaction with you and the demonstrators meant that it didn't feel so computer orientated. As long as there is someone to talk to rather than Email with questions the lab is grand.
I would suggest more designs throughout the lab. The need for writing elegant, concise and informative electronic letters is high thus I would recommend to write them more often.
There is a book by DE Thomas, P.Moorby "Verilog". They start with a big circuit and proceed slowly into the details of how the Verilog code is written to achieve the task. It gives reader an almost instant insight to what the language is capable and the "rules and regulation" associated with it. I would like to recommend that the material in the first 2 chapter be adopted. Yours faithful student, Thank you