Models

simulation: non static slice simulation: non static loop signal assignment variable assignment signal-variable assignments signal-variable for loop compare-difference width attributes - types attributes - arrays attributes of signals data types  overloaded operator definition overloaded operator call deffered constant package deffered constant call signed extension truncation signed extension truncation - package 

structure: adder 1 structure: adder 2 configuration unit for adder structure course structure 1 course structure with ALUs course structure with ALUs - split bus course-medium structures with generate ALU architecture for previous structure course-medium structures with blocks procedure calls package with subprograms function calls 

simple data flow logic structure synthesis control conditional data flow 4 to 1 multiplexer using case 4 to 1 multiplexer using conditional assignment 4 to 1 multiplexer using if .. elsif .. else .. 4 to 1 multiplexer using nested if 4 to 1 multiplexer using selected signal 8 to 1 multiplexer using case 8 to 1 multiplexer using selected signal 8 to 3 encoder using case 8 to 3 encoder using conditional assignment 8 to 3 encoder using for loop 8 to 3 encoder using if .. 8 to 3 encoder using selected signal 8 to 3 priority encoder using case 8 to 3 priority encoder using for loop 8 to 3 priority encoder using if .. 3 to 8 decoder using case 3 to 8 decoder using conditional signal assignment 3 to 8 decoder using for loop 3 to 8 decoder using for loop with exit 3 to 8 decoder using if 3 to 8 decoder using selected signal 3 to 6 enabled decoder using case (1) 3 to 6 enabled decoder using case (2) 4-bit address decoder using case 4-bit address decoder using if calls generic decoder functions generic decoder entity parameterizable decoder function package of generic decoder functions three ways to model comparator multiple comparator ALU with separate LU, AU and shifter 

simple latch inferences asynchronous latch inferences latch inference with if .. elsif (no else) latch inference with nested if latch inference with case latch inference with nested case flip-flop inference with wait and if various flip-flop inferences with reset and enable two flip-flops with combinational logic 8-bit parallel loadable LFSR 5 and 8-bit LFSRs generic n-bit LFSR 5-bit up-by-one down-by-two counter 13 count counter using a 4-bit LFSR divide by 16 asynchronous ripple counter divide by 13 asynchronous ripple counter 

FSM 1 FSM 2: separate code for sequential and combinational logic FSM 2: combined current state and next state logic FSM 2: combined next state and output logic car speed controller (1) car speed controller (2) rotor angle position controller package: rotor angle position controller using gray code FSM using sequential state assignments package defining different state assignments  FSM with Mealy outputs FSM with Moore outputs FSM with a Mealy and Moore output FSM with sequential next state logic FSM with sequential output logic - an accumulator model of a Black Jack card game machine two FSMs controlled from one master FSM three FSMs with series control between each control path modeled in one FSM data path for multiple FSM example two interactive FSMs modelling the position of two interlocked rotors  

combinational logic shifter based on six 4-1 multiplexers combinational logic shifter with in-out signals combinational logic barrel shifter two synchronous shift registers adders with comment directives for the synthesis tool adder/subtractor that accepts data on a six bit bus sequential adder: uses one full adder regardless of bit width 7x7-bit combinational multiplier of two signed numbers generic NxM shift-and-add sequential multiplier of two signed numbers generic NxM shift-and-add/subtract multiplier using Booth's algorithm 10-bit divide by 6-bit combinational divider generic NxM compare-shift-and-subtract divider of two unsigned numbers 

clock fifo RAM miscellaneous