article
Gérard Ramstein*, Frédérique Bouchard*,**, Przemyslaw Bakowski*, Vincent Stachetti** (*) SEI, IRESTE, La Chantrerie BP 60601, 44306 NANTES Cedex 03, France (**) TEMIC MATRA MHS, La Chantrerie BP 70602,, 44306 NANTES Cedex 03, France
prepared by P. Bakowski
The concern of the work presented in this paper is the development of processor models aiming at efficient simulation performances and a maximum behavioural accuracy while preserving the hardware environment of the processors, especially the VITAL environment [1]. In this context, we have developed a model of the ADSP-21020 digital signal processor from Analog Devices [2].
The low level description of the real component was available in the M language, but our model was developed in VHDL[3]. The modelling of the data path composed of the operative units (ALU, shifter, multiplier) and of the register file, which constitutes the functional kernel of the processor, has highlighted some pitfalls and fallacious ideas about data path modelling. In particular, the modelling of the floating point arithmetic with VHDL language has revealed an important semantic gap between the software defined floating point types and operators and the corresponding hardware elements.
We show that the hardware implementing IEEE 754 standard can not be modelled directly with the software defined floating point types and operators. Indeed, although VHDL aims at describing hardware, it remains a programming language belonging to the software paradigm. Contrary to the refinement of the functionalities of the hardware, the characteristics of the predefined types are very limited (they are host dependent.
For example, the exceptional conditions are only handled specifically). Although arithmetic and logic-relational packages for the floating-point were already modelled in VHDL [4], both their higher level of abstraction and the specificity of our DSP necessitate an original design. The representation of floating point was the subject of an in-depth study.
Two designs were compared, based either on integer or bit-vector coding of the floating point fields (sign, mantissa and exponent). This comparison reveals that the latter representation is preferable, in terms of legibility and efficiency.
Though constraints are tremendous on the pure functional side of the data path modelling, some freedom is possible as far as sequencing is concerned. The preservation of the programme execution model does not imply parallelism. Consequently, the high degree of parallelism introduced into the physical architecture of the processor may be almost totally suppressed in the simulation model.
This possibility allows to simplify the data path and greatly reduces the sequencing scheme of the modelled processor. In particular, almost every processor now integrates a pipeline enabling the production of a result almost every clock cycle. But these physical and performance-oriented mechanisms are not indispensable in a VHDL model, so we can play on modelling styles and on simulation semantics to imitate them. Synchronization and sequencing are the main aspects in which simplifications can be made. Besides these timing aspects, the internal structure of data path elements can also be simplified.
[1] P. Bakowski, F. Bouchard, J-P. Caïsso, F. Igier, A Case History in Building VITAL-Compliant Models, Model Generation in Electronic Design, vol. 1 of the series Current Issues in Electronic Modeling, Kluwer Academic Publishers, 1995.
[2] ADSP-21020/21010 User's Manual, Analog Devices, 1993
[3] IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-1987, The Institute of Electrical and Electronic Engineers, New York, 1988.
[4] George S. Powley, Joanne E. DeGroat, VHDL Floating Point Operations, Model Generation in Electronic Design, vol. 1 of the series Current Issues in Electronic Modeling, Kluwer Academic Publishers, 1995.