Floating Point Unit - shifter block

prepared by P. Bakowski (designer G. Ramstein)

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note : non synthetisable


The following model excecutes the shifter specification.

-- Data inputs :

-- ASX2F(39:0) x-operand input -- ASY2F(39:0) y-operand input -- ASZ2F(31:0) z-operand input

-- -- PS_AV1F ALU overflow flag from ASTAT --

-- Data outputs :

-- -- SR2F(39:0) result operand

-- -- SH_STAT2F(2:0) status output bus -- 0: shifter zero flag -- 1: shifter overflow flag -- 2: shifter sign flag

-- Control inputs :

-- -- RF_SHSD2F selects a shifter operation -- RF_ASOPD2F(7:0) ALU/shifter op code -- PS_T6D1F selects an immediate shifter operation

-- -- CK processor clock -- HLDB processor hold -- RST processor reset -- CEN bus driver enable


use work.DSP21020_pkg.all;
entity SFTR_Nty is port( ASX2F:in BV40_Typ; ASY2F:in BV40_Typ; ASZ2F:in BV32_Typ; RF_SHSD2F:in BIT; RF_ASOPD2F:in BV8_Typ; PS_T6D1F:in BIT; PS_AV1F:in BIT; CK:in BIT; HLDB:in BIT; RST:in BIT; CEN:in BIT; SR2F:out BV40_Typ; SH_STAT2F:out BV3_Typ);
end SFTR_Nty;
architecture SFTR_a of SFTR_Nty is
begin
SFTR_process : process(Ck)
begin
if Ck='1' then
-- op control
-- logic shifts
-- arithmetic shifts
-- rotates
-- bit operations
-- field operations
end if;
-- exponent extracts
-- output latches
-- output drivers
end if;
-- Ck=' '
end process;
end SFTR_a;


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