The program download initializes the Xilinx XC3042 FPGAs and downloads the configuration bitstream. The bitstream is in the form of a rawbits file, such as boris.rbt, which is the final product of the Makefile which synthesizes and maps the VHDL source files to the Xilinx format. This process is described in Appendix C. An alternate method of producing an FPGA program is to draw a Viewdraw schematic using xc3000 library components. The Xilinx tools completely automate the translation from Synopsys or Viewlogic output to FPGA files.
The download program first uses a few I/O port writes to tell the Bullwinkle control PLDs the shared memory address to use and places the state machine into Config mode (see Figure 4.4). It then writes a one or zero word to the shared memory page for each bit in the bit file, a total of 30832 writes for the XC3042 part. An I/O port write causes a Global Reset of the FPGA flip-flops, and finally Bullwinkle is placed in Acquire mode for operation to proceed.
More details on the I/O port interface to Bullwinkle can be found on Section 4.5. The XC3000 configuration process is best described in the Xilinx manuals [5,6].