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To perform a timing verfication of a Quartus® IIgenerated Verilog Output File (.vo) or VHDL Output File (.vho) and the corresponding Standard Delay Format Output File (.sdo) with the Synopsys® PrimeTime software:
To generate the Verilog Output File or VHDL Output File:
Specify EDA tool settings in the Quartus II software.
Compile the design with the Quartus II software.
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pt_shell Source the TCL Script File by typing source <design name>_pt_(v | vhd).tcl 
 at the PrimeTime shell prompt.
To set the mode of operation for the PrimeTime memory models for RAM ATOMs, use either the read_during_write mode or the no_read_during_write mode (default is read_during_write) by typing one of the following commands at the PrimeTime shell prompt:
| Device Family | Commands for Setting the Mode of Operation | 
| APEX 20K, APEX 20KC, and APEX 20KE | 
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| APEX II | 
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| ACEX® 1K or FLEX 10KE | 
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| Mercury | 
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