An Altera^® device family that is the next-generation APEX^™ system-on-a-programmable-chip (SOPC) solution. Based on the same MultiCore^™ embedded architecture as APEX 20K devices, the APEX^™ II device architecture consists of MegaLAB^™ structures, each of which contains 16 LABs (EP2A15 and EP2A25 devices) or 24 LABs (EP2A40 and EP2A70 devices) and an Embedded System Block (ESB). APEX II devices also contain a variety of other features that allow the devices to be placed directly in the data path of high-performance communication applications. The APEX II family includes the EP2A15, EP2A25, EP2A40, and EP2A70 devices.

APEX II devices support multiple protocols, for example, CSIX and POS-PHY level 4. These protocols provide high-speed communication with application-specific standard products (ASSPs), application specific integrated circuits (ASICs), and other programmable logic devices (PLDs).

APEX II devices also support High-Speed Differential Interface (HSDI). Dedicated circuitry, called True-LVDS^™ circuitry, supports LVDS, LVPECL, HyperTransport^™, and 3.3-V PCML I/O standards at speeds up to 1.0 Gbps. Four LVDS PLLs multiply reference clocks and drive high-speed differential serializer and deserializer channels. In addition, clock data synchronization (CDS) circuitry at each True-LVDS input channel corrects any fixed clock-to-data skew. All APEX II devices support 36 input channels, 36 output channels, two LVDS receiver PLLs, and two LVDS transmitter PLLs.

Flexible-LVDS^™ circuitry supports LVDS, LVPECL, and HyperTransport I/O standards at speeds up to 624 Mbps double data rate (DDR) per Flexible-LVDS channel. The EP2A15 and EP2A25 devices support 56 input and 56 output Flexible-LVDS channels. The EP2A40 and EP2A70 devices support 88 input and 88 output Flexible-LVDS channels.

The ESB of an APEX II device can be configured as product-term logic or various types of memory blocks: bidirectional dual-port RAM, dual- and single-port RAM, ROM, FIFO, and content-addressable memory (CAM). In addition, APEX II devices provide high-speed interfaces to external memory devices such as single data rate (SDR) SDRAM, DDR SDRAM and SRAM, quad data rate (QDR) SRAM, and zero bus turnaround (ZBT) SRAM.

All APEX II devices also contain General-Purpose PLLs (GPLLs), which provide enhanced ClockLock^®, ClockBoost^®, and ClockShift^™ PLL support.

You can use device migration to transfer a design between APEX II devices with equivalent pin-outs, while maintaining the same board layout and pin assignments.

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