EE 4743/6743 Digital System Design

Policy/Syllabus

Policy/Syllabus

Teaching Philosophy

This is an upper level course, and thus is taught in a different style than what I use in a lower level course. READ THIS -- it will give you a clue as to what to expect in this class.

Email List

If you have not been receiving messages from the class email list (reese-class1@erc), then IT IS VERY IMPORTANT that you get on this list! You do this via two ways:

Send email to majordomo@erc.msstate.edu with the line "subscribe reese-class1" in the body (subject does not matter)
Send email to reese@erc.msstate.edu and I will add you.

This list is where the TA and myself announce corrections to lab assignments, problems/workarounds in the software, etc. You will cost yourself a lot of hours if you do not subscribe to this list and read the messages that are sent to it.

Altera Maxplus Student Edition Software

You can get the Altera Student edition software from the CDROM that I hand out in class or via the ZIP file available from /home/reese/altera_student/maxplus2.zip (on either the ERC machines or the ECE machines). I cannot make this file available via this WWW page because it cannot be made publicy available. Use FTP to download the maxplus2.zip file (12.7 Mb) from /home/reese/altera_student. Be sure you use binary mode in downloading the file.

Once you unzip the file 'maxplus2.zip', execute the file 'install.exe' from the 'Pc/Maxplus2/' directory double clicking on it from an explorer window. If you have the CDROM, execute 'PC/Maxplus2/install.exe' directly from the CDROM.

Installing the Patch

After installation, you will also need to download the patch. You can RIGHT CLICK HERE to save it to disk; be sure to save it to the SAME directory as where you installed Maxplus2 (i.e, c:\maxplus2). Once you have saved this file, use a DOS window to execute it with the command "univers.exe -o". You can also get this patch from the WWW page referenced to during the installation process.

First Time execution

When you run maxplus2 for the first time, a license agreement will pop up in a small window. You MUST click inside of this window, and use the 'PG DN' key to page all the way down to the bottom of the agreement. At this point, you should be able to click on the "Yes" button to accept the license agreement. A window will also pop up with the software guard ID (will look like S0002XXXXX). You will need to go to THIS PAGE , enter the software guard, and fill out the form. Your authorization code will be emailed back to you very quickly; you can copy this authorization code into the appropriate window in the Maxplus2 software (will be displayed when you startup Maxplus2). After you enter the authorization code, the software should work ok. Save YOUR authorization email message from Altera somewhere safe!!! If you have installation problems, I would like to see this message FIRST before I help you.

If you used the 'maxplus2.zip' file, after installation you can delete the 'Pc/...' directory tree that was created after unzipping.

Altera Maxplus Professional Edition Software

Once you install the software, the first time you execute it you will see message about a missing or corrupted license file. Use the Options -> License file menu choice to set the path to the license file server. Use that path given in class. WARNING -- Maxplus2 will take about 3-4 minutes to start because it has to download licenses.

Labs

Homeworks

Any files referenced in the labs can be directly copied or ftp'ed from "~reese/EE4743/labs/" on leto.ece.msstate.edu. Some students have had trouble accessing these from the HTML hyperlinks.

Lecture Supplements

Fixed Point arithmetic, Saturating adders
FPGA Families Summaries.
You should also look at the data sheets.
Test #1 Review (HTML)
Test #1 (Microsoft Word)
FPGA Timing Models
You should also look at the data sheets.
Introduction to Pipelining
Altera Timing Model Details
Postscript file for FIR filter FSM example
Datapath Design, Part I
Datapath Design, Part II
RAM Zeroing Operation Example, zip file, Implementation 1. This is an implementation of the example given in the Datapath design notes, Part I. This implementation uses mostly LPMs.
RAM Zeroing Operation Example, zip file, Implementation 2. This is an implementation of the example given in the Datapath design notes, Part I. This implementation uses mostly VHDL.
RAM Zeroing Operation Example, zip file, Implementation 3. This is an implementation of the example given in the Datapath design notes, Part I. This illustrates the use of structural VHDL to replace the top-level schematic of the second implementation. Uses two VHDL files.
RAM Zeroing Operation Example, zip file, Implementation 4. . This is an implementation of the example given in the Datapath design notes, Part I. This illustrates simply declaring the RAM component instantiation into the same VHDL file that contains the FSM code and other datapath components. This shows that you can mix component instantiations in with RTL code.
Test #2 Review (HTML)
Test #2 (Microsoft Word)

Topic Coverage by Week

Week 1: Intro to Maxplus2
Week 2: VHDL Combinational Logic Introduction
Week 3: Saturating arithmetic, begin talking about Implementation technologies (Full Custom, Standard Cells, Gate Arrays, FPGAs, CPLDs, PLDs).
Week 4: FPGA Families
Week 5: FPGA Families, Timing, Test #1
Week 6: FPGA Timing Models, start VHDL for Sequential Logic
Week 7: FSMs in VHDL
Week 8: FSM/Datapath Design in VHDL

Data Sheets

Altera Flex10K FPGA
Altera Max 7000A FPGA
Xilinx Virtex FPGA
Actel MXDS FPGA
Cypress Ultra37000 CPLD
Cypress PAL20 PLD
Texas Instruments Logic Selection Guide , lists all of the low voltage IO families, discussions of them.

Sample Tests

Misc

CRC Faq
CRC Explained... Original source is here

To read PDF documents on the Sun systems, do "swsetup acrobat", then do "acroread documentname".

VHDL Examples

Click HERE for the VHDL examples from the notes. These have checked to work with Altera Maxplus2.

UP1 Board

Professor Jim Hamblen's (Ga Tech) UP1 Board page Look here for interesting project ideas, neat implementations, and miscellaneous tips.
Ga Tech Page that discusses use of Video module and keyboard module for UP1 Board.
Zip file that contains video/keyboard modules referenced above.
Improved keyboard function that has a little better performance (important for large designs if using the onboard 25Mhz clock as system clock for keyboard module. The original module had marginal timing and would sometimes fail if integrated into a larger design.)
Zip archive containing the SOF file for 'circles' game (requires keyboard, VGA monitor). 'Circles' is a Nim variant - instructions for the game are displayed on the video screen. Spring 99 class project.

Using the Altera UP1 Board

Make sure that the jumpers on the board are set correctly. Look at this document for an explanation of the jumpers. Look at pages 5,6 at the description of the jumper settings and make sure that you can program the Flex10K device.
Connect power to your board, and the byteblaster cable to the parallel port and to your board.
Start Maxplus2, and click on the ByteBlaster icon or the "Programmer" choice under the Max+plusII menu. If the Hardware setup window does not appear, then access this via "Options -> Hardware Setup". Choose ByteBlaster, and make sure that LPT1 port is selected. Close the Hardware setup menu.
Under the "JTAG" menu, make sure that "Multi-Device Jtag Chain" is checked. Then under the "JTAG" menu, execute the "Multi-Device JTAG Chain Setup". When this menu pops up, click on "Select Programming File" and browse to the .SOF file that you want to download. Click on "Add", then exit by clicking on "Ok". There should be only ONE programming file selected.
In the "Programmer" popup menu, click on "Configure", and you should see the download completion bar progress from 0% to 100%. Your design is now downloaded.
If you are running NT, you must install the ByteBlaster driver. Access the Multimedia icon under the Control Panel, and add an "Unknown device"; point the installation program at the maxplus2/drivers directory. Choose the "ByteBlaster" when the popup menu appears, and the installation will complete. You will need to reboot.

Maxplus Oddities, Error Messages

This is a list of oddities/errata/weird_stuff that you need to be aware of when using the Maxplus software:

.TDF file extension: When you edit a text file using Maxplus, the default extension is ".TDF". Do NOT use this for a VHDL code - the default compiler invoked on a ".TDF" is not the VHDL compiler. Use a ".vhd" file extension for VHDL files.
If you get an error message about 'tri-state outputs' during compilation, this means that you have two outputs tied together (probably have mistakenly named two busses the same name ).
Student Edition Installation under Win98: Many people have installed the Student Edition under Win98 with no problems. However, the following problem occurred on a Pentium 130Mhz, 32Mb RAM system running Win98 - everytime the installation procedure was attempted, a system error occurred that would terminate the installation. Many different things were tried, including shutting down all starup programs, copying the "Pc/Maxplus2 directory tree to the C: drive before installation, etc. We finally got it work by first copying the "Pc/" directory on the Maxplus CDROM to drive C:, booting in Safe Mode, and then doing the installation (Safe mode does not have a CDROM driver so that is why the "Pc/" directory had to be copied first). After the installation completed, the machine was booted normally and all worked ok.
Student Edition, "Partitioner Error" Under the Student edition, if a design won't fit (i.e. a 16-bit multiplier in a Max7000 part), then you will occasionally get a 'Internal Partitioner Error' instead of a 'Design does not Fit' message. Try mapping the design to a Flex10K family part.
Student Edition, Synthesis Problem with Finite State Machines, Conditional outputs in Processes. These two files, fsmbad.vhd and fsmgood.vhd illustrate a synthesis problem with the student edition V7.21 (the problem does not occur in the Professional edition). The lecture notes use the style that is shown in the 'bad' example, so be SURE to use the style in the 'good' example if you are using the Student edition. This is actually a symptom of a larger problem as shown by test_bad.vhd and test_good.vhd . In the student edition V7.21, if you have a conditional output in an 'if' statement inside of a CASE statement, the output will have a latch synthesized on it if the 'if' statement does not have an 'else' clause EVEN if the output is previously assigned a default value. The professional edition generates the correct logic (no latch). BE CAREFUL OF THIS!!!! This bug is tough to spot!! Try to avoid conditional outputs inside of case statementts if you are using Student V7.21 or put them in concurrent statements outside of the process.
Here are two more examples that correspond to the FSM defined in the Datapath notes . The first file is the recommended method for writing FSMs if you are using the Student edition V7.21. The second file follows the style discussed in the notes, and works fine with the professional edition.
Student Edition, Compare operation. This is from James Hamblen, Professor at Ga Tech. The only big VHDL problem issue that I have come across deals with '<' or>' compare ops. It does not select signed correctly and seems to always use unsigned compare operations (i.e. it ignores your signed library statement). This is fixed only in the latest pro version.