EE 4743 Test Topics #1 (THIS IS NOT INCLUSIVE!)

You are responsible for anything discussed in class, or in the Lab. Because it is impossible to list all of the topics we have discussed, I am listing the most important ones. These are the ones that I will concentrate on, but if I have left something out of this list, I reserve the right to ask you about it!

1. Be able to read a combinational VHDL model and plot a truth table.
2. Be able to write a VHDL model for a simple combinational model.
3. Know the structure of a ripple carry adder.
4. Know how to design a saturating adder, both signed and unsigned.
5. Know what fixed point format means for unsigned numbers. Know how to translate back and forth.
6. Be able to discuss different implementation technologies - full custom, standard cell, gate array, FPGA, CPLD, PLD. Know what each is, and some of the Pros/Cons of each.
7. Be familiar with the Altera Flex 10k, Xilinx Virtex, and Actel MX families. Know what a Look Up Table is for definining combinational logic. Know the difference between monolithic SRAM blocks and SRAM built from look up tables. Know what cascade chain, carry chains are.
8. Understand the operation of Labs 1, 2, 3.
9. Know what combinational logic delays, what longest path means, what shortest path means.