EE 4743/6743
Computer Aided Design of Digital Systems
Class Policy and Syllabus (Spring '99)

Bob Reese
Simrall 335 (I am very seldom in this office)
Engineering Research Center 231 (Office phone 325-3670)

Office Hours: Immediately after class in Simrall,
ERC office, MWF 1:30-2:30, call first before coming over
Email address: reese@erc.msstate.edu

Temporary WWW Page: www.erc.msstate.edu/~reese/EE4743 Here
Old WWW Page (Dr. Russ). www.erc.msstate.edu/~russ/classes/CADD.html Here

Textbooks:
1. Course Notes - See Dr. Russ Homepage
2. VHDL for Programmable Logic - Kevin Skahill, Cypress Semiconductor
3. Many other in-class handouts

Grade Determination:
(3) Exams 70%
(1) Final 10%
Labs 20%
____
100%

Grade assignment is on a 10-point scale.

If you can’t find me in my Simrall office then I am probably over at the Engineering Research Center. Before you visit me at the ERC, set up an appointment via phone or electronic mail (do not come over to the ERC without phoning first because I might be in a meeting or out of the office and you will have wasted a trip).

The CAD Lab is considered an OPEN lab which means you can work on your assignment anytime the lab is open and you can find a free machine. Your assigned lab period is a time in which you will be GUARANTEED a machine; you should go to the lab during your assigned lab period because the instructor will be available for questions and help. Typically, a lab will be due 1 to 2 weeks after it is handed out. You should start on the lab IMMEDIATELY since the assignment will generally take longer than the assigned lab period and competition for the lab machines will become fierce as the due date draws near. It will not be unusual for a new lab assignment to overlap a previous lab assignment. I do not assign homework in this class because of the amount of work required on the lab assignments. Doing a good job on the lab assignments directly affects your test grade because test questions are related to work done in the lab.

I spend most of my time in my ERC office; the remote location of the ERC makes quick office visits inconvenient. PLEASE feel free to use the phone and/or email to contact me; it is often easier than driving out to the ERC. If you have a problem with a design, an easy thing to do is to phone me from the CAD lab and let us work out the problem while you are sitting in front of a workstation.

Exit campus on Lee Blvd going north. Turn left on to Hwy 82 (heading towards Starkville) at the Highway Patrol office. Turn right at the MSU Research Park entrance. Turn right at the first intersection and follow the boulevard around - take the first right (there will be sign that says MSU/NSF Engineering Research Center). Follow the road until it takes a left into a big parking lot - this is the ERC parking lot. Park in the front and enter through the double glass doors. Turn left once inside and follow the corridor until it gets to the main ’research hall’ which has cubicles in the middle and offices down either side. I am in office 231 which is about 2/3 thirds of the way down on the ’east’ side.

Shuttle Bus Service

There is also a shuttle bus service from the campus to the ERC. The bus is marked as the Blue route, and the schedule is:

• Leave Cafeteria (5 min after hour), Arrive ERC (15 min after hour), Leave ERC (20 min after hour), Arrive Cafeteria (30 min after hour)
  

Occasionally, we have a problem in this course with Academic Dishonesty. Academic Dishonesty is when you present some other person's work as your own. The following is my definition of academic dishonesty:

• Looking at or copying any material from another student. This material could be schematics, VHDL files, simulation files, etc. The person providing this material would also be guilty of academic dishonesty.

You may DISCUSS external homeworks, and verbally answer questions about homeworks from other students. You may not SHOW your homework to another student, or provide an 'old copy' as an example!!!!

If I find a student guilty of academic dishonesty, expect an F in the course and an academic dishonesty claim to go into your permanent academic record.

COURSE SOFTWARE

We will be using the Altera Maxplus software package for the first time in this course. Previous semesters have used the Viewlogic software package. One of the main reasons I have decided to switch to the Maxplus package is that it will be much easier for you to use it on your home PC. There is a free Student Edition (version 7.21) or Maxplus II Baseline (version 9.1). Either can be downloaed from www.altera.com. The Maxplus II Baseline is more up-to-date than the Student Edition, but will only work for 6 months. Both versions require you to fill out an on-line form before downloading (and getting a license). We also have the software available on the Unix workstations in the first floor computer lab, and the PC's in the 3^rd floor PC lab.

Because this is the first semester that we will be using the MAXplus software, EXPECT problems! A golden rule to remember is that CAD software is NEVER perfect, and there will always be problems to work around!!!!

Week 2 : VHDL Synthesis, Finite State Machine design

Week 3 : Implementation Technologies, PLDs, ACTEL FPGAs

Week 4 : Timing Analysis, Speedup Techniques (TEST #1)

Week 5 : Fast Adder techniques

Week 6 : Design For Test

Week 7 : Two-phase versus Single Phase Design

Week 8 : Xilinx FPGA’s

Week 9 : Standard Cell Implementation (TEST #2)

Week 10 : Structural VHDL, VHDL Modeling, Top-Down Design

Week 11 : Project Discussion

Week 12 : Communicating Finite State Machines

Week 13 : Datapaths, CAD Data Formats

Week 14 : High Level Synthesis

Week 15 : High Level Synthesis (TEST #3).

Week 16 : Review for Final

#1 Powerview Schematic Capture/Simulation

#2 VHDL Synthesis Lab (Combinatorial, Sequential)

Four labs dealing with implementations of digital filters.

A course project will also be assigned and several class lectures devoted to it. The implementation of the course project will be the topic of 2-3 lab assignments.