Semi-Automated IMINT Processing System (SAIP) Case Study

1.0 Introduction

The DARPA Rapid Prototyping of Application Specific Signal Processor (RASSP) program goal was to dramatically reduce the time and effort required to develop, produce, and maintain complex embedded digital signal processing (DSP) systems. Lockheed Martin Advanced Technology Laboratories (ATL) was required to assess the RASSP process improvements by performing design benchmarks. The goal of Benchmark 4 (BM4) was to dramatically upgrade the HighClass (target classifier) portion of DARPA's SAIP systemusing the tools and techniques developed under the RASSP Program. The goal of the upgrade was to increase the processor density (i.e. Gflops/cu.ft.) by more than 100x while demonstrating the capabilities, benefits and improvements afforded by RASSP's innovative hardware/software codesign methodology.

ATL used the iterative hardware/software co-design process and advanced CAD tools developed under the RASSP program to accomplish the SAIP HighClass processor development effort. The SAIP HighClass subsystem requirements were provided by MIT Lincoln Laboratory (MIT-LL), the original developers of the SAIP HighClass subsystem, in the form of executable specifications as well as a written RASSP Benchmark 4 Technical Descriptionspecification. In addition to the performance, size, weight and power improvements, the upgrade was required to interface with the existing SAIP hardware/software environment using a standard ATM interface. As part of the development effort hardware/software co-design processes and performance modeling techniques were applied to develop, analyze and validate architecture tradeoffs at key decision points throughout the program. The design and tradeoff efforts were accomplished using a combination of ATL's GEDAE™ software development and autocoding tools, Omniview’s Cosmos modeling tool and ATL developed QuickVHDL models. Architecture tradeoffs included cost analysis using the RASSP Integrated System Tools. The key factor in achieving the throughput and size improvements was the optimization the SAIP HighClass High Definition Imaging (HDI) and Mean Square Error (MSE) target classification functions of the hardware/software implementation of emerging COTS DSP products. Initial efforts focused on understanding the requirements and performing algorithm tradeoffs to improve the efficiency for the embedded DSP hardware. The 20,000 lines of source code in the executable specification were originally implemented in MATLAB, translated to C, and modified for use in the DARPA SAIP Advanced Concept Technology Demonstration (ACTD) program. As part of ATL's functional analysis process significant improvements were made in the computational design which lead to a 2.7X reduction in the processing throughput requirements. These redesigned algorithms were captured graphically using the RASSP Data Flow Software Development Process and ATL's GEDAE™ software development tools. Using GEDAE™, the final HDI and MSE software for the selected DSP boards were automatically generated and distributed to the individual Sharc processors. This not only simplified the final hardware/ software integration and test, but provided a low cost/risk path for future software and/or hardware product extensions and improvements.

The results of the SAIP BM4 development efforts were significant. Through the process of algorithm implementation tradeoffs, architecture analysis, and performance modeling, an all COTS hardware architecture, based on commercial VME Sharc DSP boards (72 total processors), was selected, eliminating the need for a custom hardware design. Using performance modeling results, ATL was able to validate the use of a lower cost, higher density Sharc board product which reduced hardware costs to 1/3 of our initial estimate. The resulting design achieved the 7x through put improvement, doubled the number of target templates, and achieved greater than 100X improvement in overall throughput density. Finally, capturing of the system software in GEDAE™ provides the potential for future COTS model year upgrades as the SAIP program proceeds.

The remainder of this case study describes in more detail the SAIP application and requirements, the design processes used to develop the BM4 hardware prototype, and the lessons learned and results achieved by applying the RASSP hardware/ software codesign and virtual prototyping techniques, graphical software development and autocoding tools and emerging COTS components. The case study is divided into the following sections relating more details and insights into the BM4 SAIP HighClass processor development efforts.

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