Figure 4.2.1 Parallel ASIC and Subsystem Development
"We consider both ASIC- and system-level worst-case debugging necessary because simulators cannot predict every possible problem that may occur."
Engineering parts facilitate physically characterizing the ASIC both alone and in its target system. In the context of engineering parts, characterization is a set of tests used on fabricated parts to determine performance parameters of the ASIC and its system. These tests should cover all anticipated electrical and environmental conditions.
We consider both ASIC- and system-level worst-case debugging necessary because simulators cannot predict every possible problem that may occur once an ASIC is actually fabricated and used. For example, a fabrication process may have changed since the last time model libraries were updated or the designer may have inadvertently left out a crucial modeling step during simulation. Engineers cannot detect all of these problems until they test the fabricated part.
Using engineering parts rather than flight parts for debugging the ASIC and its system saves substantial time and money. Fabricating engineering parts along with flight parts assures that they will represent the flight parts in form, fit and function (see "Part Acceptance Approach" in Chapter 1 of this section). However, engineering parts do not go through expensive screening or quality conformance inspection (QCI), which can save up to four months in a part delivery schedule.
We recommend testing engineering parts before screening flight parts. If failures during engineering part testing suggest ASIC redesign or refabrication, flight parts are rejected. Thus, the ASIC manager should direct the vendor to wait until engineering parts are verified before beginning the screening of flight parts.
Designers and other user engineers investigate specific design and manufacturing problems with an ASIC by using it in its target system, testing it stand-alone or by reviewing vendor test data. Anomalous variations can occur in the vendor's process yet remain undetected during the vendor's process characterization; these variations still affect a particular ASIC design's performance.
There may be systemic problems with packaging and assembly. The need to investigate design-dependent issues, such as SEE sensitivity, depends on how well the cell library has been characterized. For more on cell library evaluation, see Section Two: Chapter 4.
Designers and other user engineers should test engineering parts to verify and fine tune AC and DC parameter margins that simulation predicts. In particular they should test DC margins for parameters such as leakage current, which are highly sensitive to process variations. Other specifications that may need modification include:
Modifying parameters, however, requires an engineering part sample size large enough to acquire meaningful statistics. Engineers should document any margin requirement changes in the detailed specification. Modifying margin requirements from their simulation values should improve the specified performance of the ASIC. The margin values suggested by simulation are conservative and probably wider than necessary to account for all process variations.
Figure 4.2.1 Parallel ASIC and Subsystem Development
Engineering parts can also be characterized individually to "grade" flight part screening. Examining engineering parts determines whether the fabrication process has produced failure mechanisms that the set of screens planned for the flight parts will not detect. Tests to perform such examination include:
If the process and design rules have not been deliberately designed for latchup immunity, extensive latchup testing should be performed. Latchup may depend upon design rules, such as spacing, but with modern processes it is usually not lot dependent. If there is a narrow margin between claimed total ionizing dose (TID) tolerance and the expected TID environment, we recommend TID testing on engineering parts and on samples of flight parts, especially when using processes not specifically designed to be rad-hard. Otherwise, TID testing is not normally necessary.
Understanding failure mechanisms may also require failure analysis (see Appendix Four: "Failure Analysis"). Uncovering serious failure mechanisms may entail adding tests to the flight part screening programs that will detect these newly-discovered failure mechanisms, or it may entail modifying the vendor's process to eliminate the failure mechanisms from forming.
Finally, the initial application of test vectors to engineering parts will most likely reveal one or more problems. One source of these problems arises from incompatibilities in moving vectors from the simulation environment to the tester environment; ASIC simulation behavior that differs from behavior of the ASIC part may be another source. Resolving all such problems and insufficiencies during engineering part acceptance ensures that a complete and effective test vector set can be used during flight part acceptance.
Ideally, ASIC development occurs in parallel with its subsystem, as shown in Figure 4.2.1, Parallel ASIC and Subsystem Development. ASIC margins are then set in context with overall subsystem margin requirements. After fabricating and testing engineering parts, designers perform a subsystem characterization. Here designers test a board-level prototype at worst-case margin limits for system performance. If the CAD system analysis was inaccurate or incomplete, the system may fail and require redesign at the ASIC or board level.
Figure 4.2.2 shows the subsystem characterization flow described below.
Figure 4.2.2 Subsystem Characterization
To determine appropriate action due to an ASIC failure, failure analysis must identify whether the failure is ASIC defect- or subsystem-induced. If defect-induced, simply replace the ASIC (after performing the appropriate ASIC-level analysis to screen for that defect in these replacement devices). However, if the failure was subsystem-induced, whether due to an ASIC failure or some other failure, subsystem handling and/or requirements need changing (usually parametric requirements). If modifying subsystem requirements implies modifying ASIC margin requirements, then designers must determine whether ASIC or subsystem redesign is necessary.
Performing an ASIC test-to-failure on an engineering part may help determine whether the existing ASIC can support these new margin requirements without redesign and refabrication.
To determine ASIC performance limits, engineers can use "test- to-failure" conditions, which involve electrically or environmentally stressing a part until it fails. The results may provide a comparison between ASICs or it can tell ASIC designers they can widen ASIC margins without redesign.
During "test-to-failure" characterizations, engineers often compile "delta" measurements to understand how a part degrades over time due to electrical and environmental stresses. "Deltas" are parameter changes between successive stresses, such as reductions in operating voltage. Such stresses include radiation doses, supply voltages, absolute temperatures or temperature cycles. Graphs of ASIC parameters as a function of electrical or environmental stress are often referred to as "SHMOO" plots.
Though helpful in designing more reliable flight parts, engineering part characterization cannot predict flight part reliability. Engineering parts lack the reliability assurance that flight parts obtain through screening and QCI. Statistically, engineering parts will have a shorter expected life span and a higher chance of early failure than flight parts, since they include some defective parts that flight part screening would reject.
Now you may jump to: