Old 6809 Flex Computer Project
SBC09CPU Features are:
2MHz HD63B09 or compatible CPU (8Mhz Clock) - 3MHz HD63C09 ??? (12MHz)
4 x 32 PIN DIP sockets for 27040/29F040/HM62512 EPROM/FLASH/RAM
6522 VIA printer port using DB25 connector (26 pin header)
MC146818 real time clock
Am85C30 dual serial port with 10 pin headers for DB9 connectors
Single +5V supply rail.
Use of two XC95108 CPLDs
- Dynamic Address translation (1Mb max)
- Address decoding
- Interrupt Request Controller
- Floppy Disk Controller Timing WD2795 or WD2797 floppy disk controller
(Inverting or non inverting data bus through programmable CPLD)
Provision for High Density 5.25" and 3.5" floppies (equivalent to 8" drives)
Support for 360RPM 5.25" floppies and 300RPM floppies.
SS-50C form factor and bus interface
SBC09CPU.GIF which includes CPU, Memory, CPLD, DAT and bus buffering
SBC09FDC.GIF which include FDC (WD2797), CPLD and Interface buffering
SBC09IO.GIF include RTC (MC146818), Parallel IO (6522 VIA), and serial IO (Am85C30)
SBC09PCB.PS postcript component overlay
Notes and Ramblings on the Design:
Flex System Register definitions
Flex Multi Tasking IO Kernel
Revison History:
18th October 2001
I tarted up the system register definitions. I've put the mask bits of the Chip Select
registers in the same byte as the address compare bit, although I'm not sure this is
a good idea as it would be nice to have a Chip Select Enable bit.
I've added CPU clock divider bits to the wait state generator. At Diego Trampas
suggestion I have included a "Fuse Counter" and System / User mode to disable
system register and DAT access.
The DAT will now be mapped into the top 256 bytes of memory rather than using
a bank select register (16 pages of 16bytes). The system registers are mapped in
7 bytes of the next 256 bytes below that. The Fuse counter will be used to latch
the DAT page number (User number) to perform task switched. The DAT output
will be disabled on reset (pulled high bu pullups), but the top 4K of MEM3 will be
mapped into CPU memory to execute system startup and program the DAT and
system registers.
I will include a 26 pin header for IO expansion so that those who want a 16 bit IDE
port can create a paddle board with a CPLD and 40 pin IDE header. There is not
enough space on the board at the moment to add IDE directly.
Some consideration has been given to smaller calendar clock chips such as the 8pin
MK41T56 with IIC bus as the MC146818A is physically large. The MK41T56
has battery backup circuitry, which reduces the requirement on the uP supervisor chip
however the MC146818 has a programable periodic interupt output which is lacking
on most calendar chips. This feature is very useful for a multi tasking timer interrupts.
Also the bus access of the MC146818A makes it very easy to access battery backed
RAM. Use accumulator B to write the RAM Address and read and write memory
using accumulator A. On reset there will be no RAM mapped into the system, and it
may be desirable to use battery backed up parameters to configure the system registers
and DAT RAM.
15th Octrober 2001
I've updated the SBC09CPU.GIF circuit to replace the address buffers with address
tranceivers as per the suggestion of Joseph Lang. I have re-arranged the pin outs of
the CPLD, yet again to include DBDIR (Data Bus Direction), DBEN* (Data Bus Ebable)
ABDIR (Address Bus Direction) and ABEN* (Address Bus Enable).
I have changed (B)MRDY to go through the CPLD to the processor, allowing inclusion
of a wait state generator for external bus access cycles. To make room for these pins,
I have had to remove some of the pins from the DAT RAM and two of the switch inputs.
I have also changed the crystal clock to 24MHz to allow divide by 3 for an 8MHz clock
for the CPU. PCLK has been adde to the CPLD for this purpose.
14th October 2001
I have significantly revamped the 6809 design
It is now mounted on a SS-50C card format for use in a SWTPC
25th November 2000
1. PB7, CB1 and CB2 of the 6522 have been connected to pins 23, 24 and 25 of the
DB25 connector respectively. The idea is that these pins can be set as inputs and grounded
if a centronic connector is used.2. The programmable FDC clock circuit has been changed so that the 12MHz crystal
oscillator is only needed for 360RPM drives reading low density (360K) floppies.
U23 is changed from a 74HC393 to a 74HC390. The 2MHz/1MHz FDC clocks are
derived from the CPU E signal.3. A pin header has been added for I/O port expansion.
23th November 2000
1. I have removed the Z8530 as realisticaly I am unlikely to spend any time
hacking packet radio code for an old 2MHz 6809. The idea was to just drop
in a ROM such as SWTBUG and get the board to run with a minimum of fuss.2. U10 and U11 have been replaced with a MAX232 as I have them in the
junk box and the MC145406/7s may be expensive. The board only has one
serial port now so the MC145406 is redundant anyway.3. The Address decoding GAL22V10 has been replaced with discrete logic.
Again, the reason is ease of construction. Although the GAL saves on component
count, they are expensive and require special programming. This restrict the
Addressing of the board to the standard SWTPC memory map, but I don't
see the board being used for anything else.4. The MAX1232 Watchdog reset circuit is a nice device, but it has been replaced
with a simpler 74LS14 schmitt buffer, again to keep the cost down.5. Only one baudrate jumper area is used to save space on the board. Since
I have done away with the Z8530, there is no longer a requirement for two baud
rates.
Flex CPU Section
Address Map:
$0000 - $7FFF RAM0
$8000 - $DFFF RAM1
$E000 - $EFFF I/O$E000 - $E00F ACIA$F000 - $FFFF ROM
$E010 - $E01F FDC$E010 - $E013 Expansion 1 (Port 4)$E020 - $E02F VIA Parallel (Printer) Port.
$E014 - $E017 Floppy Motor Register
$E018 - $E01B Floppy Controller Registers
$E01C - $E01F Expansion 2 (Port 7)
$E030 - $E03F Real Time Clock
A switch is provided on A12 of the ROM so it can be used as two separate 4Kbyte monitor ROMs.
A12 of the ROM is either connected to ground or the A12 pin of the CPU which may be held high
for ROM access. This is desirable if you want to boot OS9 as well as FLEX9 with separate Boot programs.Note that this design does not support memory paging.
Interrupts:
RESET - Power on reset and watchdog timer
IRQ - ACIA/RTC/VIA
FIRQ - Floppy Disk Controller
NMI - Interrupt button
Serial Ports:
1. DCD (N/C)
2. RXD Input
3. TXD Output
4. DTR Output (Tied to RTS)
5. GND
6. N/C
7. RTS Output
8. CTS Input
9. N/CParrallel (Printer) Port:
A Synertek/Rockwell 6522 VIA is used for the printer port. The DB25 connector is designed to be as compatible
with the IBM / Centronics printer port as possible. ie. Port A of the VIA is used for the data lines and Port B is
used for the control and status lines. Note that not all 8 of the Port B signals are available on the printer connector.
It is up to the programmer to initialise the 6522 VIA to operate the printer correctly.1. STROBE* (CA2) Output
2. DB0 (PA0) Bidirectional
3. DB1 (PA1) Bidirectional
4. DB2 (PA2) Bidirectional
5. DB3 (PA3) Bidirectional
6. DB4 (PA4) Bidirectional
7. DB5 (PA5) Bidirectional
8. DB6 (PA6) Bidirectional
9. DB7 (PA7) Bidirectional
10. ACK* (CA1) Input
11. BUSY (PB4)
12. EMPTY (PB5)
13. SELECT (PB6)
14. FEED* (PB0) Output
15. ERROR* (PB1)
16. INIT* (PB2)
17. SEL IN* (PB3)
18. GND
19. GND
20. GND
21. GND
22. GND
23. GND (PB7)
24. GND (CB1)
25. GND (CB2)
I/O Expansion Header
1 - GND
2 - GND
3 - D0
4 - D1
5 - D2
6 - D3
7 - D4
8 - D5
9 - D6
10 - D7
11 - A0
12 - A1
13 - Port 4 CS* ($E010)
14 - Port 7 CS* ($E01C)
15 - R/W*
16 - E
17 - RD*
18 - WR*
19 - IRQ*
20 - N/C
21 - VCC (+5V)
22 - VCC (+5V)
23 - VDD (+12V)
24 - VDD (+12V)
25 - N/C
26 - N/C
Flex Floppy Disk Controller:
The Floppy disk controller circuit has been whole heartedly ripped off from Michael Holley,
with a few minor corrections and improvements:Data Bus Polarity:
The WD2795 has an inverted data bus, where as the WD2797 is non inverting. I have added a data
bus tranceiver (U14) which can be a 74HCT640 for the inverted data bus, or a 74HCT245 for non
inverting data buses (WD2797).The tricky bit with the Wester Digital Chips is to meet the data hold time. I have not looked closely
at the timing specs, but I am hoping that there is enough capacitance on the 6809 bus to hold the
tranceivers in the correct state. I have used the R/W* signal for the directionand the FDC chip select
line to enable the transceivers. These signals should not be gated with the E clock if the hold time
is to be observed. The RD* and WR* signals are generated by the standard R/W* and E signals.
High Density Drives:
The floppy controller is designed exclusively for 5.25" and 3.5" drives. ie, it only uses a 34 pin IDC
connector. The 8/5* select signal is used for High Densisty recording, rather than 8" drives.
For 300RPM drives, a clock rate of 1MHz or 1.2 MHz is used for low density (360K) floppies
and 2MHz is used for High Density (1.2M / 1.44M) floppies.Pin 2 of IBM compatible floppy drives is used for reduced write current (at least thats what it says in
my manuals). I have connected this pin to the 8/5* signal so that reduced write current is used on
all high density disks.
Changes to Michael Holley's circuit
Michael's circuit was only a draft as of 12th November 2000. I have changed the following:1. Optional inverting / non inverting data tranceiver
2. Programmable Clock for 1MHz, 1.2 MHz and 2MHz
3. Side Select generated either by the controller or the Motor Register.
4. Reduced write current signal on pin 2 derived from 8/5*.
5. Direction & Step pins swapped (either my mistake or Michaels)
6. Output pins fed back to Motor status register
7. FIRQ* generated by DRQ* signal rather than IRQ*/NMI* from INTRQ*
8. Motor register is at $E014 Controller at $E018 - Michael I think yours is wrong ...
9. I have removed many of the jumpers to simplify things.Apart from that they are identical. Michael's shematic is better layed out and has more consistant
component symbols.34 Pin Floppy Drisk connector
1 - GND
2 - Reduced Write Current (Out)
3 - GND
4 - HLD (Not Used)
5 - GND
6 - DS3 Drive Select 3 (Out)
7 - GND
8 - Index Pulse (IP) (In)
9 - GND
10 - DS0 Drive Select 0 (Out)
11 - GND
12 - DS1 Drive Select 1 (Out)
13 - GND
14 - DS2 Drive Select 2 (Out)
15 - GND
16 - Motor On (Out)
17 - GND
18 - DIR Direction (Out)
19 - GND
20 - STEP Stepping Pulse (Out)
21 - GND
22 - WDAT Write Data (Out)
23 - GND
24 - WG Write Gate (Out)
25 - GND
26 - TR00 Track 0 (In)
27 - GND
28 - WRPT Write Protect (In)
29 - GND
30 - RDAT Raw Read Data (In)
31 - GND
32 - SS Side Select (Out)
33 - GND
34 - RDY Ready (Not Used)
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