Doulos VHDL Training, Comprehensive VHDL for FPGA/ASIC

Recent innovations include FPGA-specific coding and optimization strategies for the following devices:

• Altera FLEX(R) families
• Altera MAX(R) families
• Xilinx XC4000
• Xilinx XC3000
• Xilinx XC9500
• Lattice
• Actel 3200DX
• Actel MX series

The course is organised as two modules, Introduction to VHDL (2 days) and Further VHDL (3 days). You may attend these modules at separate times or complete the course in one week. Introduction to VHDL provides a good grounding in VHDL and synthesis, ideal for engineers evaluating the technology, or looking for cost effective preparation for small FPGA/PLD projects. Building on the two day Introduction, Further VHDL provides additional essential preparation for large-scale design projects, emphasizing VHDL style for synthesis, writing test benches, and project organization.

Over 50% of course time is devoted to practical workshops using leading simulation and synthesis tools. A wide range of tools are made available on all public courses. On site courses can be run with tools of the client's choice.

What The Course Will Tell You

• How VHDL fits into the ASIC/FPGA design flow
• How to use the VHDL language for hardware design and logic synthesis
• How to write good VHDL test benches to verify your designs
• How to organize and manage a VHDL project
• How to avoid common mistake with VHDL and synthesis

• Introduction
  • Scope and application of VHDL
  • Design flow
  • Levels of abstraction
  • Synthesis technology
  • Benefits of VHDL
  • Sources of information on VHDL
• Methodology
  • The high level design methodology
  • Design flow using VHDL and synthesis
  • Capturing an ASIC design using VHDL
  • Functional validation of a VHDL specification
  • Writing and using test benches, defining stimulus and analyzing results
  • Multiple representations of a design, switching between multiple representations
  • Refining data types
  • Gate level simulation and VHDL, VITAL (VHDL Initiative Toward ASIC Libraries)
  • Comparing results across levels of abstraction
• VHDL Style
  • Choosing the best VHDL styles for synthesis and simulation
  • Getting the right hardware
  • Avoiding synthesis pitfalls
  • Writing VHDL for simulation efficiency
• Project management
  • Organizing a VHDL project
  • Using VHDL libraries and configurations
  • VHDL and teamworking, coding standards
  • Source file organization, VHDL data management and control
  • Functional validation techniques
• Making Effective use of VHDL
  • Describing combinational logic
  • Synchronous and asynchronous sequential logic
  • Finite state machines, counters, and memories
  • Writing parameterized, generic descriptions to enhance reusability
  • Reading and writing text files from VHDL

Comprehensive VHDL naturally splits into two course streams, usually taken together, but if you are unable to attend the full course...

Introduction to VHDL (Days 1 and 2) gives a good grounding in VHDL and synthesis, ideal for engineers evaluating the technology and covers the following VHDL language topics:

Entities, architectures, libraries, use, ports, signals, components, port maps, default configuration, variables, constants, STD_LOGIC_1164, enumeration types, concurrent assignments, processes, sensitivity, assignments, if, case, loop, wait, operators, names and numbers, slices, concatenation, type conversion, synthesis attributes.

Further VHDL (Days 3, 4 and 5) provides additional essential preparation for large FPGA and ASIC design projects, emphasizing VHDL style for synthesis, writing test benches and project organization, covering the following language topics:

Port association, buffer ports, generics, generate, conditional and selected assignments, assertions, integer subtypes, array types, type attributes, array attributes, aggregates, qualified expressions, subprograms, overloading, package bodies, configurations, TEXTIO, type TIME, resolution limit, floating types, delta delay, inertial and transport delay, drivers, initialization.