Doulos VHDL Training, Altera Focus

Comprehensive VHDL for FPGA/ASIC provides the opportunity for the course attendee to focus on Altera-specific VHDL coding and synthesis techniques in order to exploit FLEX and MAX architectures to the best advantage. The focus is not only on device architecture features, but also on the use of MAX+PLUS II and third-party synthesis tools to further increase your utilization of the target architecture.

Our focus on Altera-specific training covers the following areas:

• Exploiting the FLEX Architecture
• Exploiting the MAX Architecture
• MAX+PLUS II Optimization Strategies
• Third Party Synthesis Tool Optimization Strategies
  • Leonardo
  • Synopsys FPGA Compiler
  • Synplify

Our course leaders apply their hardware design experience with their RTL synthesis knowledge and home in on the optimal use of FLEX and MAX devices. They will go beyond the conventional approach to VHDL coding and synthesis techniques in order to provide you with the most relevant and up-to-date information for exploiting FLEX and MAX devices.

In many of the course workshops you will be able to apply the Altera-specific techniques that you learn to exploit the target architecture through VHDL and synthesis. In addition, you are provided with the following documentation:

• Using Altera MAX+PLUS II Software Tool Tour
• Exploiting Altera Architectures Technology Guide

What you will learn from the course

• How to target Altera devices from a VHDL-based design flow using generic synthesis tools
• How to use the VHDL language to exploit Altera’s FLEX and MAX architectures
• How to use the MAX+PLUS II tools to optimize to the target device
• How to organize and manage a VHDL-based FLEX/MAX design project
• How to avoid common mistakes when coding VHDL for Altera devices using any synthesis tool
• How to dramatically cut device and system cost (typically around 70%) simply by knowing the FLEX- and MAX-specific tips and tricks you will learn from Doulos

Just some of the Altera-specific topics you will cover

• Coding for LPM blocks
• LPM optimization
• Performance improvement beyond LPM optimization
• System design performance improvements

Our course leaders are not satisfied with presenting an overview of Altera’s technology, they will give you the in-depth focus on exploiting the FLEX and MAX architectures from VHDL coding that you need.

Remember! Not only will you learn how to take advntage of MAX and FLEX features, you will also learn how to avoid the pitfalls of VHDL and synthesis in order to maximise your productivity.

Comprehensive VHDL for Systems
Advanced VHDL for Synthesis

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This page was last updated 4^th December 1997

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