Design Implementation (cont.)
Until you get more confident with VHDL, should use as many LPM components as you can
- Can easily examine input/outputs to LPMs in waveform viewer so makes it easier to debug
Always use a VERY LONG clock cycle to start out with so that you do not encounter timing problems
- To be absolutely safe, make external inputs change on the falling edge if your internal logic is rising edge triggered (this gives you 1/2 clock of setup time).