Comments on Model Hierarchy

• Often created separate entities for purposes of hardware mapping

  • ALU split into alulogic and addsub
    • alulogic is random logic
    • addsub implementation technology dependent (I.e. X4000 fastcarry chain versus standard cell CLA implementation)
  • Register file split into rfcore (16 GPRs) and rflogic
    • X4000E CLB DPRAM good for RFCORE impl.

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