Quartus® II support for elaboration and execution of VHDL designs is described below. Section numbers match those in both the IEEE Std 1076-1987 and the IEEE Std 1076-1993 versions of the IEEE Standard VHDL Language Reference Manual.
| Section | VHDL Construct | VHDL 1987 Support Note (1) | VHDL 1993 Support Note (1) |
|---|---|---|---|
| 12.1 | Elaboration of a Design Hierarchy | Supported. | Supported. |
| 12.2 | Elaboration of a Block Header | Supported as defined below. | Supported as defined below. |
| 12.2.1 | The Generic Clause | Supported. | Supported. |
| 12.2.2 | The Generic Map Clause | Supported. | Supported. |
| 12.2.3 | The Port Clause | Supported as described in Design Entities & Configurations. | Supported as described in Design Entities & Configurations. |
| 12.2.4 | The Port Map Clause | Supported. | Supported. |
| 12.3 | Elaboration of a Declarative Part | Supported. | Supported. |
| 12.3.1 | Elaboration of a Declaration | Supported. | Supported. |
| 12.3.1.1 | Subprogram Declarations & Bodies | Supported as described in Subprograms & Packages. | Supported as described in Subprograms & Packages. |
| 12.3.1.2 | Type Declarations | Supported as described in Types and Declarations. | Supported as described in Types and Declarations. |
| 12.3.1.3 | Subtype Declarations | Supported as described in Declarations. | Supported as described in Declarations. |
| 12.3.1.4 | Object Declarations | Supported as described in Declarations. | Supported as described in Declarations. |
| 12.3.1.5 | Alias Declarations | Supported as described in Declarations. | Supported as described in Declarations. |
| 12.3.1.6 | Attribute Declarations | Supported as described in Declarations. | Supported as described in Declarations. |
| 12.3.1.7 | Component Declarations | Supported. | Supported. |
| 12.3.2 | Elaboration of a Specification | Supported as described in Specifications. | Supported as described in Specifications. |
| 12.3.2.1 | Attribute Specification | Supported as described in Specifications. | Supported as described in Specifications. |
| 12.3.2.2 | Configuration Specification | Supported as described in Specifications. | Supported as described in Specifications. |
| 12.3.2.3 | Disconnection Specification | Ignored, as described in Specifications. | Supported as described in Specifications. |
| 12.4 | Elaboration of a Statement Part | Supported. | Supported. |
| 12.4.1 | Block Statements | Supported as described in Concurrent Statements. | Supported as described in Concurrent Statements. |
| 12.4.2 | Generate Statements | Supported as described in Concurrent Statements. | Supported as described in Concurrent Statements. |
| 12.4.3 | Component Instantiation Statements | Supported as described in Concurrent Statements. | Supported as described in Concurrent Statements. |
| 12.4.4 | Other Concurrent Statements | Supported as described in Concurrent Statements. | Supported as described in Concurrent Statements. |
| 12.5 | Dynamic Elaboration | Not supported | Not supported |
| 12.6 | Execution of a Model | Not supported. | Not supported. |
| 12.6.1 (1993) | Drivers | Supported. (Formerly section 9.2.1 in IEEE Std 1076-1987.) | Supported. |
| 12.6.1 (1987) 12.6.2 (1993) |
Propagation of Signal Values | Not supported. | Not supported. |
| 12.6.2 (1987) 12.6.3 (1993) |
Updating Implicit Signals | Not supported. | Not supported. |
| 12.6.3 (1987) 12.6.4 (1993) |
The Simulation Cycle | Not supported. | Not supported. |
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