VHDL

Concurrent Statements

Quartus® II support for concurrent statements is described below. Section numbers match those in both the IEEE Std 1076-1987 and the IEEE Std 1076-1993 versions of the IEEE Standard VHDL Language Reference Manual.

Section VHDL Construct VHDL 1987 Support     Note (1) VHDL 1993 Support     Note (1)
9.1 Block Statement Supported. Supported.
9.2 Process Statement Supported. Supported.
9.2.1 (1987) Drivers Supported. Supported. (Reassigned to section 12.6.1 in IEEE Std 1076-1993.)
9.3 Concurrent Procedure Call Statements Not supported. Not supported.
9.4 Concurrent Assertion Statement Supported. Concurrent Assertion Statements are passive. Supported. Concurrent Assertion Statements are passive.
9.5 Concurrent Signal Assignment Statements Supported. Supported.
9.5.1 Conditional Signal Assignment Supported. Supported.
9.5.2 Selected Signal Assignment Supported. Supported.
9.6 Component Instantiation Statement Supported. Supported.
9.6.1 Instantiation of a Component Supported. Supported.
9.6.2 (1993) Instantiation of a Design Entity n/a Not supported.
9.7 Generate Statement Supported. "For" Generate Statements must have locally static bounds, and "If" Generate Statements must have locally static conditions. Supported. "For" Generate Statements must have locally static bounds, and "If" Generate Statements must have locally static conditions.


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