Primitives

The Quartus^® II software provides a variety of primitive functions for circuit design. AHDL, Verilog HDL , and VHDL logical operators, ports, and some statements, as well as Verilog HDL gate primitives, replace primitives in AHDL, Verilog HDL, and VHDL files. As a result, AHDL, Verilog HDL, and VHDL primitives are a subset of those available for Block Design Files (.bdf), as shown below.

Primitive/Port Interconnections
Unused Inputs to Primitives, Megafunctions & Macrofunctions

Buffer Primitives
`CARRY`	`LCELL`
`CARRY_SUM`	`OPNDRN`
`CASCADE`	`SOFT`
`CLKLOCK`	`TRI`
`EXP`	`WIRE` (Block Design Files only)
`GLOBAL`	`ROW_GLOBAL`

Flipflop & Latch Primitives
`DFF`	`LATCH`
`DFFE`	`SRFF`
`DFFEA`	`SRFFE`
`JKFF`	`TFF`
`JKFFE`	`TFFE`

Input & Output Primitives/Ports
`BIDIR` or `INOUT`
`INPUT` or `IN`
`OUTPUT` or `OUT`

Logic Primitives
`AND`	`NOR`
`BAND` (Block Design Files only)	`NOT`
`BNAND` (Block Design Files only)	`OR`
`BNOR` (Block Design Files only)	`VCC` (Block Design Files only)
`BOR` (Block Design Files only)	`XNOR`
`GND` (Block Design Files only)	`XOR`
`NAND`

Other Primitives (Block Design Files only)
`CONSTANT`
`PARAM`
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AHDL Function Prototypes are not needed for primitives in Text Design Files (.tdf) and Verilog Design Files (.v). In AHDL, however, you can redefine the calling order of the primitive inputs by including a Function Prototype Statement for the primitive in the TDF.
Verilog HDL also includes built-in gate primitives that must be used instead of their corresponding Quartus^® primitives. Go to Using a Verilog HDL Gate Primitive for more information.

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