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To use the Model Technology^™ ModelSim^®-Altera^® (OEM) software to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components:

1. If you have not already done so, perform 2. Set Up a Project with the ModelSim-Altera Software.

2. If your design contains the altgxb megafunction, to map to the precompiled Stratix^™ GX functional simulation model libraries:

   1. Choose New > Library (File menu). The Create a New Library dialog box appears.

   2. Under Create, select a new library and a logical mapping to it.

   3. In the Library Name box, type altgxb.

   4. In the Library Maps to box, specify the \quartus\eda\sim_lib\modelsim\<verilog or vhdl>\altgxb\ directory.

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

3. For VHDL 93-compliant designs, to map the design libraries to your work library:

1. Choose New > Library (File menu). The Create a New Library dialog box appears.

2. Under Create, select a new library and a logical mapping to it.

3. Type lpm in the Library Name box, and type \<ModelSim-Altera install directory>\altera\vhdl\220model\ in the Library Maps to box, and click OK.

4. Repeat steps 3a and 3b to map altera_mf to the \<ModelSim-Altera install directory>\altera\altera_mf\ directory.

   If you want to use VHDL 87-compliant simulation libraries, you must map lpm and altera_mf to the \<ModelSim-Altera install directory>\altera\220model_87\ and \<ModelSim-Altera install directory>\altera\altera_mf_87\ directories, respectively.

4. To compile the Verilog or VHDL Design Files and test bench files (if you are using a test bench):

   1. Choose Compile (Compile menu).

   2. In the Library list of the Compile HDL Source Files dialog box, select the work library.

   3. In the File name list, type the directory path and file name of the Verilog or VHDL Design File.

      or

      In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog or VHDL Design File.

   4. Click Compile.

   5. Repeat steps 4b to 4d to compile the test bench file(s).

   6. If you are performing a functional simulation of an ARM^®-based Excalibur^™ design, repeat steps 5b to 5d to compile the appropriate ARM-based Excalibur simulation model wrapper file.

   7. Click Done.

5. To load the design:

   1. Choose Simulate (Simulate menu). The Simulate dialog box appears.

   2. If you are simulating a Verilog design, to specify the ModelSim precompiled libraries:

      1. Click the Libraries tab.

      2. In the Search Libraries (-L) box, click Add.

      3. Specify the \<ModelSim-Altera install directory>\altera\verilog\220model\ directory.

      4. Repeat step c to add the \<ModelSim-Altera install directory>\altera\verilog\altera_mf\ directory.

      5. Click OK.

   3. In the Name list, click the + icon to expand the work directory.

   4. Select the top-level design file to simulate.

   5. Click Add.

   6. Click Load.

6. Perform the functional simulation in the ModelSim-Altera software.

If you are simulating an ARM-based Excalibur design, the bus functional model generates the output.dat bus functional model simulation file. Refer to ModelSim software documentation for more information on how to view and interpret the results of the simulation.

7. To continue with the ModelSim-Altera simulation flow and perform a timing simulation, return to one of the following steps:

   • 2. Set Up a Project with the ModelSim-Altera Software
   • 2. Set Up a Project with the ModelSim-Altera Software (Command-Line)

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