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The following simulation models and wrapper files are provided for performing a functional or timing simulation of an ARM®-based Excalibur™ design in other EDA simulation tools.
The following bus functional model wrapper files are located in the <Quartus® II installation directory>\eda\sim_lib\excalibur\lpm directory:
File Name |
Description |
alt_exc_stripe_bfm.v |
Simulation model wrapper file for functional simulation of a Verilog HDL design with the bus functional model. |
alt_exc_stripe_bfm.vhd |
Entity declaration for the model wrapper for functional simulation of a VHDL design with the bus functional model. |
alt_exc_stripe_arch_bfm.vhd |
Architecture declaration file for the model wrapper for functional simulation of a VHDL design with the bus functional model. |
The following Excalibur Stripe Simulator (ESS) model wrapper files are located in the <Quartus II installation directory>\eda\sim_lib\excalibur\ directory:
File Name |
Description |
\lpm\alt_exc_stripe_ess.v |
Simulation model wrapper file for fast functional simulation or functional co-simulation of a Verilog HDL design with the ESS model. |
\lpm\alt_exc_stripe_ess.vhd |
Simulation model wrapper file for fast functional simulation or functional co-simulation of a VHDL design with the ESS model. |
\ess_hdl\ess_hdl.v |
Contains the Verilog HDL modules used by the ESS model to model the interface between the PLD and the C model of the Excalibur embedded processor stripe. |
\ess_hdl\ess_hdl.vhd |
Contains the VHDL components used by the ESS model to model the interface between the PLD and the C model of the Excalibur embedded processor stripe. |
The following full stripe model wrapper files and simulation models are located in the <Quartus II installation directory>\eda\sim_lib\excalibur\stripe_model_nt\modelgen\models\<epxa1 | epxa4 | epxa10>\r0\mti_modelsim_<verilog or vhdl>\ directory:
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You can use the full stripe model to simulate Verilog designs with the ModelSim® PE/SE (non-OEM) and ModelSim-Altera® (OEM) software, and use the full stripe model to simulate VHDL designs with the ModelSim SE software |
File Name |
Description |
apex20ke_stripe.v |
Contains the full stripe model wrapper for timing simulation of a Verilog HDL design |
apex20ke_stripe.vhd |
Contains the full stripe model wrapper for timing simulation of a VHDL design |
alt_exc_stripe.v |
Contains the full stripe model wrapper for functional simulation of a Verilog HDL design |
alt_exc_stripe.vhd |
Contains the full stripe model wrapper for functional simulation of a VHDL design |
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