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A design should not contain an asynchronous load signal if the design's target device does not have a logic cell that directly supports the implementation of the signal. When the target device does not have one logic cell that directly supports the implementation of signal, the Quartus^® II software uses multiple logic cells to implement the signal. However, the multiple logic cells may cause glitches and other problems in the design.

If the target device does not support the implementation of an asynchronous load signal with one logic cell, you can change the device you are targeting. For example, if you are using an APEX^™ 20KE device, you can change the device to a FLEX 10KE device.

This rule applies only to designs that the Logic Synthesizer has processed, but the Fitter has not processed, during a compilation.

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