See Also

A design should not contain SR latches, which are structures where two NOR or NAND gates (which the Quartus^® II software implements in logic cells) are cross-coupled using combinatorial loops that drive the output of one gate to an input of the other gate. SR latches can cause glitches and ambiguous timing in a design, which makes timing analysis of the design more difficult.

The Design Assistant also generates this rule for SR latches that are part of more sophisticated latches that the Design Assistant cannot identify.

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